On Thu, 12 Aug 2021 at 13:08, Alexandre IOOSS <erdn...@crans.org> wrote: > > > On 8/12/21 11:33 AM, Peter Maydell wrote: > > It is quite common for a clock tree to involve possibly programmable > > clock multipliers or dividers, where the frequency of a clock is for > > instance divided by 8 to produce a slower clock to feed to a > > particular device. > > > > Currently we provide no convenient mechanism for modelling this. You > > can implement it by having an input Clock and an output Clock, and > > manually setting the period of the output clock in the period-changed > > callback of the input clock, but that's quite clunky. > > > > This patch adds support in the Clock objects themselves for setting a > > multiplier or divider. The effect of setting this on a clock is that > > when the clock's period is changed, all the children of the clock are > > set to period * multiplier / divider, rather than being set to the > > same period as the parent clock. > > > > Signed-off-by: Peter Maydell <peter.mayd...@linaro.org> > > --- > > docs/devel/clocks.rst | 23 +++++++++++++++++++++++ > > include/hw/clock.h | 29 +++++++++++++++++++++++++++++ > > hw/core/clock-vmstate.c | 24 +++++++++++++++++++++++- > > hw/core/clock.c | 29 +++++++++++++++++++++++++---- > > 4 files changed, 100 insertions(+), 5 deletions(-) > > > > diff --git a/docs/devel/clocks.rst b/docs/devel/clocks.rst > > index 956bd147ea0..430fbd842e5 100644 > > --- a/docs/devel/clocks.rst > > +++ b/docs/devel/clocks.rst > > @@ -260,6 +260,29 @@ clocks get the new clock period value: *Clock 2*, > > *Clock 3* and *Clock 4*. > > It is not possible to disconnect a clock or to change the clock connection > > after it is connected. > > > > +Clock multiplier and divider settings > > +------------------------------------- > > + > > +By default, when clocks are connected together, the child > > +clocks run with the same period as their source (parent) clock. > > +The Clock API supports a built-in period multiplier/divider > > +mechanism so you can configure a clock to make its children > > +run at a different period from its own. If you call the > > +``clock_set_mul_div()`` function you can specify the clock's > > +multiplier and divider values. The children of that clock > > +will all run with a period of ``parent_period * multiplier / divider``. > > +For instance, if the clock has a frequency of 8MHz and you set its > > +multiplier to 2 and its divider to 3, the child clocks will run > > +at 12MHz. > > + > > +You can change the multiplier and divider of a clock at runtime, > > +so you can use this to model clock controller devices which > > +have guest-programmable frequency multipliers or dividers. > > This looks nice! > Does this imply that if I am going to implement the STM32 RCC (Reset and > Clock Controller) device, then I should use this new feature?
I haven't looked at the RCC spec in detail, but yeah, I'd expect that you'd have a device with one (or perhaps more) input clocks and a lot of output clocks, and as the guest writes to registers that set divider/multiplier settings you'd use clock_set_mul_div() to configure the appropriate output clocks. -- PMM
