Reviewed-by: Huacai Chen <chenhua...@loongson.cn>
On Fri, Aug 13, 2021 at 7:01 PM Philippe Mathieu-Daudé <f4...@amsat.org> wrote:
>
> Document the cores on which each Loongson-3A CPU is based (see
> commit af868995e1b, "target/mips: Add Loongson-3 CPU definition").
>
> Signed-off-by: Philippe Mathieu-Daudé <f4...@amsat.org>
> ---
> target/mips/cpu-defs.c.inc | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/target/mips/cpu-defs.c.inc b/target/mips/cpu-defs.c.inc
> index e03b2a998cd..c6ab3af190e 100644
> --- a/target/mips/cpu-defs.c.inc
> +++ b/target/mips/cpu-defs.c.inc
> @@ -805,7 +805,7 @@ const mips_def_t mips_defs[] =
> .mmu_type = MMU_TYPE_R4000,
> },
> {
> - .name = "Loongson-3A1000",
> + .name = "Loongson-3A1000", /* Loongson-3A R1, GS464-based */
> .CP0_PRid = 0x6305,
> /* 64KB I-cache and d-cache. 4 way with 32 bit cache line size. */
> .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) |
> @@ -835,7 +835,7 @@ const mips_def_t mips_defs[] =
> .mmu_type = MMU_TYPE_R4000,
> },
> {
> - .name = "Loongson-3A4000", /* GS464V-based */
> + .name = "Loongson-3A4000", /* Loongson-3A R4, GS464V-based */
> .CP0_PRid = 0x14C000,
> /* 64KB I-cache and d-cache. 4 way with 32 bit cache line size. */
> .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) |
> --
> 2.31.1
>
