On 8/12/21 11:33 AM, Peter Maydell wrote:
> Wire up the refclk for the msf2 SoC.  This SoC runs the refclk at a
> frequency which is programmably either /4, /8, /16 or /32 of the main
> CPU clock.  We don't currently model the register which allows the
> guest to set the divisor, so implement the refclk as a fixed /32 of
> the CPU clock (which is the value of the divisor at reset).
> 
> Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>

Reviewed-by: Damien Hedde <damien.he...@greensocs.com>

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