Apply new gdbstub interfaces we added previously to support both little and big endian guest debugging for RISC-V. And enable the TARGET_SWICHABLE_ENDIANNESS option.
Signed-off-by: Changbin Du <changbin...@gmail.com> --- configs/targets/riscv32-softmmu.mak | 1 + configs/targets/riscv64-softmmu.mak | 1 + target/riscv/gdbstub.c | 12 ++++++------ 3 files changed, 8 insertions(+), 6 deletions(-) diff --git a/configs/targets/riscv32-softmmu.mak b/configs/targets/riscv32-softmmu.mak index d8b71cddcd..7f02e67c72 100644 --- a/configs/targets/riscv32-softmmu.mak +++ b/configs/targets/riscv32-softmmu.mak @@ -3,3 +3,4 @@ TARGET_BASE_ARCH=riscv TARGET_SUPPORTS_MTTCG=y TARGET_XML_FILES= gdb-xml/riscv-32bit-cpu.xml gdb-xml/riscv-32bit-fpu.xml gdb-xml/riscv-64bit-fpu.xml gdb-xml/riscv-32bit-virtual.xml TARGET_NEED_FDT=y +TARGET_SWICHABLE_ENDIANNESS=y diff --git a/configs/targets/riscv64-softmmu.mak b/configs/targets/riscv64-softmmu.mak index 7c0e7eeb42..c3e812495c 100644 --- a/configs/targets/riscv64-softmmu.mak +++ b/configs/targets/riscv64-softmmu.mak @@ -3,3 +3,4 @@ TARGET_BASE_ARCH=riscv TARGET_SUPPORTS_MTTCG=y TARGET_XML_FILES= gdb-xml/riscv-64bit-cpu.xml gdb-xml/riscv-32bit-fpu.xml gdb-xml/riscv-64bit-fpu.xml gdb-xml/riscv-64bit-virtual.xml TARGET_NEED_FDT=y +TARGET_SWICHABLE_ENDIANNESS=y diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c index a7a9c0b1fe..d639cea859 100644 --- a/target/riscv/gdbstub.c +++ b/target/riscv/gdbstub.c @@ -42,10 +42,10 @@ int riscv_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) /* discard writes to x0 */ return sizeof(target_ulong); } else if (n < 32) { - env->gpr[n] = ldtul_p(mem_buf); + env->gpr[n] = gdb_read_regl(mem_buf); return sizeof(target_ulong); } else if (n == 32) { - env->pc = ldtul_p(mem_buf); + env->pc = gdb_read_regl(mem_buf); return sizeof(target_ulong); } return 0; @@ -81,11 +81,11 @@ static int riscv_gdb_get_fpu(CPURISCVState *env, GByteArray *buf, int n) static int riscv_gdb_set_fpu(CPURISCVState *env, uint8_t *mem_buf, int n) { if (n < 32) { - env->fpr[n] = ldq_p(mem_buf); /* always 64-bit */ + env->fpr[n] = gdb_read_reg64(mem_buf); /* always 64-bit */ return sizeof(uint64_t); /* there is hole between ft11 and fflags in fpu.xml */ } else if (n < 36 && n > 32) { - target_ulong val = ldtul_p(mem_buf); + target_ulong val = gdb_read_regl(mem_buf); int result; /* * CSR_FFLAGS is at index 1 in csr_register, and gdb says it is FP @@ -118,7 +118,7 @@ static int riscv_gdb_get_csr(CPURISCVState *env, GByteArray *buf, int n) static int riscv_gdb_set_csr(CPURISCVState *env, uint8_t *mem_buf, int n) { if (n < CSR_TABLE_SIZE) { - target_ulong val = ldtul_p(mem_buf); + target_ulong val = gdb_read_regl(mem_buf); int result; result = riscv_csrrw_debug(env, n, NULL, val, -1); @@ -145,7 +145,7 @@ static int riscv_gdb_set_virtual(CPURISCVState *cs, uint8_t *mem_buf, int n) { if (n == 0) { #ifndef CONFIG_USER_ONLY - cs->priv = ldtul_p(mem_buf) & 0x3; + cs->priv = gdb_read_regl(mem_buf) & 0x3; if (cs->priv == PRV_H) { cs->priv = PRV_S; } -- 2.32.0