This patch starts the counter negative EBB support by enabling PMC1 counter negative overflow when PMC1 is counting cycles.
A counter negative overflow happens when a performance monitor counter reaches the value 0x80000000. When that happens, if counter negative condition events are enabled in that counter, a performance monitor alert is triggered. For PMC1, this condition is enabled by MMCR0_PMC1CE. Cycle counting is done by calculating elapsed time between the time the PMU started to run and when the PMU is shut down. Our clock is fixed in 1Ghz, so 1 cycle equals 1 nanoseconds. The same idea is used to predict a counter negative overflow: calculate the amount of nanoseconds for the timer to reach 0x80000000, start a timer with it and trigger the performance monitor alert. If event-based exceptions are enabled (bit MMCR0_EBE), we'll go ahead and fire a PPC_INTERRUPT_PMC. A new function 'start_cycle_count_session' was added to encapsulate the most common steps of cycle calculation: redefine base time and start overflow timers. This will avoid code repetition in the next patches. Counter overflow for the remaining counters will be added shortly. Signed-off-by: Daniel Henrique Barboza <danielhb...@gmail.com> --- target/ppc/cpu.h | 1 + target/ppc/power8_pmu.c | 96 +++++++++++++++++++++++++++++++++-------- 2 files changed, 79 insertions(+), 18 deletions(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 535754ddff..b9d5dca983 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -352,6 +352,7 @@ typedef struct ppc_v3_pate_t { #define MMCR0_PMCC PPC_BITMASK(44, 45) /* PMC Control */ #define MMCR0_FC14 PPC_BIT(58) #define MMCR0_FC56 PPC_BIT(59) +#define MMCR0_PMC1CE PPC_BIT(48) #define MMCR1_PMC1SEL_SHIFT (63 - 39) #define MMCR1_PMC1SEL PPC_BITMASK(32, 39) diff --git a/target/ppc/power8_pmu.c b/target/ppc/power8_pmu.c index a57b602125..d10f371b5f 100644 --- a/target/ppc/power8_pmu.c +++ b/target/ppc/power8_pmu.c @@ -33,6 +33,8 @@ static void update_PMC_PM_CYC(CPUPPCState *env, int sprn, env->spr[sprn] += time_delta; } +#define COUNTER_NEGATIVE_VAL 0x80000000 + static uint8_t get_PMC_event(CPUPPCState *env, int sprn) { int event = 0x0; @@ -116,30 +118,88 @@ static void update_cycles_PMCs(CPUPPCState *env) } } +static int64_t get_CYC_timeout(CPUPPCState *env, int sprn) +{ + int64_t remaining_cyc; + + if (env->spr[sprn] >= COUNTER_NEGATIVE_VAL) { + return 0; + } + + remaining_cyc = COUNTER_NEGATIVE_VAL - env->spr[sprn]; + return remaining_cyc; +} + +static bool counter_negative_cond_enabled(uint64_t mmcr0) +{ + return mmcr0 & MMCR0_PMC1CE; +} + +/* + * A cycle count session consists of the basic operations we + * need to do to support PM_CYC events: redefine a new base_time + * to be used to calculate PMC values and start overflow timers. + */ +static void start_cycle_count_session(CPUPPCState *env) +{ + uint64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); + uint64_t timeout; + + env->pmu_base_time = now; + + /* + * Always delete existing overflow timers when starting a + * new cycle counting session. + */ + timer_del(env->pmu_intr_timers[0]); + + if (!counter_negative_cond_enabled(env->spr[SPR_POWER_MMCR0])) { + return; + } + + if (!pmc_is_running(env, SPR_POWER_PMC1)) { + return; + } + + if (!(env->spr[SPR_POWER_MMCR0] & MMCR0_PMC1CE)) { + return; + } + + switch (get_PMC_event(env, SPR_POWER_PMC1)) { + case 0xF0: + case 0x1E: + timeout = get_CYC_timeout(env, SPR_POWER_PMC1); + break; + default: + return; + } + + timer_mod(env->pmu_intr_timers[0], now + timeout); +} + static void cpu_ppc_pmu_timer_cb(void *opaque) { PowerPCCPU *cpu = opaque; CPUPPCState *env = &cpu->env; - uint64_t mmcr0; - - mmcr0 = env->spr[SPR_POWER_MMCR0]; - if (env->spr[SPR_POWER_MMCR0] & MMCR0_EBE) { - /* freeeze counters if needed */ - if (mmcr0 & MMCR0_FCECE) { - mmcr0 &= ~MMCR0_FCECE; - mmcr0 |= MMCR0_FC; - } - /* Clear PMAE and set PMAO */ - if (mmcr0 & MMCR0_PMAE) { - mmcr0 &= ~MMCR0_PMAE; - mmcr0 |= MMCR0_PMAO; - } - env->spr[SPR_POWER_MMCR0] = mmcr0; + if (!(env->spr[SPR_POWER_MMCR0] & MMCR0_EBE)) { + return; + } - /* Fire the PMC hardware exception */ - ppc_set_irq(cpu, PPC_INTERRUPT_PMC, 1); + if (env->spr[SPR_POWER_MMCR0] & MMCR0_FCECE) { + env->spr[SPR_POWER_MMCR0] &= ~MMCR0_FCECE; + env->spr[SPR_POWER_MMCR0] |= MMCR0_FC; } + + update_cycles_PMCs(env); + + if (env->spr[SPR_POWER_MMCR0] & MMCR0_PMAE) { + env->spr[SPR_POWER_MMCR0] &= ~MMCR0_PMAE; + env->spr[SPR_POWER_MMCR0] |= MMCR0_PMAO; + } + + /* Fire the PMC hardware exception */ + ppc_set_irq(cpu, PPC_INTERRUPT_PMC, 1); } void cpu_ppc_pmu_timer_init(CPUPPCState *env) @@ -182,7 +242,7 @@ void helper_store_mmcr0(CPUPPCState *env, target_ulong value) if (!curr_FC) { update_cycles_PMCs(env); } else { - env->pmu_base_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); + start_cycle_count_session(env); } } } -- 2.31.1