Am 21.10.2011 08:58, schrieb Peter Maydell: > On 20 October 2011 23:51, Andreas Färber <andreas.faer...@web.de> wrote: >> Renesas announced >> the R-Car H1 this week, a SoC with one SH4A core and four ARM Cortex-A9 >> cores. > > Does it expose the SH4 to apps/OSes, or is it mostly used for > power management or similar ignorable duties?
The predecessors were all SuperH based only, and the ARM cores don't seem to have VFPv3 so the SH4A would feature a 128-bit FPU. As for what automative customers may do with it once available, I have no clue. My focus is on investigating where QEMU has architectural shortcomings or undocumented assumptions blocking embedded development and addressing these. > (For several > of the ARM boards we currently just ignore the fact that the real > h/w has a Cortex-M3 doing power management type stuff.) Mind to share which boards? I'm only aware of the NXP LPC43xx asymmetric SoC (Cortex-M4 + Cortex-M0), which still is in development stage. The datasheet doesn't really enlighten me how such a combo is supposed to work in shared memory: Do all ARM cores share a reset vector (or what you call it on arm) so that one has to branch based on CPUID to do different tasks on different cores? Andreas
