Thank you for your quick comments. > Question: For testing, did you dump all the ID registers on this > model and compare them with a dump of ID registers from real > hardware? If so, that would be good info to put in the commit > message or at least the cover letter.
Yes, it has been tested and confirmed. We will re-post the v6 patches later, adding the information you mentioned. Best regards. > -----Original Message----- > From: Andrew Jones <drjo...@redhat.com> > Sent: Monday, August 30, 2021 5:40 PM > To: Ishii, Shuuichirou/石井 周一郎 <ishii.shuuic...@fujitsu.com> > Cc: peter.mayd...@linaro.org; qemu-...@nongnu.org; qemu-devel@nongnu.org > Subject: Re: [PATCH v5 1/3] target-arm: Add support for Fujitsu A64FX > > On Mon, Aug 30, 2021 at 05:28:18PM +0900, Shuuichirou Ishii wrote: > > Add a definition for the Fujitsu A64FX processor. > > > > The A64FX processor does not implement the AArch32 Execution state, so > > there are no associated AArch32 Identification registers. > > > > For SVE, the A64FX processor supports only 128,256 and 512bit vector > > lengths. > > > > Signed-off-by: Shuuichirou Ishii <ishii.shuuic...@fujitsu.com> > > --- > > target/arm/cpu64.c | 48 > > ++++++++++++++++++++++++++++++++++++++++++++++ > > 1 file changed, 48 insertions(+) > > > > diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index > > 2f0cbddab5..15245a60a8 100644 > > --- a/target/arm/cpu64.c > > +++ b/target/arm/cpu64.c > > @@ -841,10 +841,58 @@ static void aarch64_max_initfn(Object *obj) > > cpu_max_set_sve_max_vq, NULL, NULL); } > > > > +static void aarch64_a64fx_initfn(Object *obj) { > > + ARMCPU *cpu = ARM_CPU(obj); > > + > > + cpu->dtb_compatible = "arm,a64fx"; > > + set_feature(&cpu->env, ARM_FEATURE_V8); > > + set_feature(&cpu->env, ARM_FEATURE_NEON); > > + set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); > > + set_feature(&cpu->env, ARM_FEATURE_AARCH64); > > + set_feature(&cpu->env, ARM_FEATURE_EL2); > > + set_feature(&cpu->env, ARM_FEATURE_EL3); > > + set_feature(&cpu->env, ARM_FEATURE_PMU); > > + cpu->midr = 0x461f0010; > > + cpu->revidr = 0x00000000; > > + cpu->ctr = 0x86668006; > > + cpu->reset_sctlr = 0x30000180; > > + cpu->isar.id_aa64pfr0 = 0x0000000101111111; /* No RAS Extensions > */ > > + cpu->isar.id_aa64pfr1 = 0x0000000000000000; > > + cpu->isar.id_aa64dfr0 = 0x0000000010305408; > > + cpu->isar.id_aa64dfr1 = 0x0000000000000000; > > + cpu->id_aa64afr0 = 0x0000000000000000; > > + cpu->id_aa64afr1 = 0x0000000000000000; > > + cpu->isar.id_aa64mmfr0 = 0x0000000000001122; > > + cpu->isar.id_aa64mmfr1 = 0x0000000011212100; > > + cpu->isar.id_aa64mmfr2 = 0x0000000000001011; > > + cpu->isar.id_aa64isar0 = 0x0000000010211120; > > + cpu->isar.id_aa64isar1 = 0x0000000000010001; > > + cpu->isar.id_aa64zfr0 = 0x0000000000000000; > > + cpu->clidr = 0x0000000080000023; > > + cpu->ccsidr[0] = 0x7007e01c; /* 64KB L1 dcache */ > > + cpu->ccsidr[1] = 0x2007e01c; /* 64KB L1 icache */ > > + cpu->ccsidr[2] = 0x70ffe07c; /* 8MB L2 cache */ > > + cpu->dcz_blocksize = 6; /* 256 bytes */ > > + cpu->gic_num_lrs = 4; > > + cpu->gic_vpribits = 5; > > + cpu->gic_vprebits = 5; > > + > > + /* Suppport of A64FX's vector length are 128,256 and 512bit only */ > > + aarch64_add_sve_properties(obj); > > + bitmap_zero(cpu->sve_vq_supported, ARM_MAX_VQ); > > + set_bit(0, cpu->sve_vq_supported); /* 128bit */ > > + set_bit(1, cpu->sve_vq_supported); /* 256bit */ > > + set_bit(3, cpu->sve_vq_supported); /* 512bit */ > > + > > + /* TODO: Add A64FX specific HPC extension registers */ } > > + > > static const ARMCPUInfo aarch64_cpus[] = { > > { .name = "cortex-a57", .initfn = aarch64_a57_initfn }, > > { .name = "cortex-a53", .initfn = aarch64_a53_initfn }, > > { .name = "cortex-a72", .initfn = aarch64_a72_initfn }, > > + { .name = "a64fx", .initfn = aarch64_a64fx_initfn }, > > { .name = "max", .initfn = aarch64_max_initfn }, > > }; > > > > -- > > 2.27.0 > > > > For the SVE stuff, > > Reviewed-by: Andrew Jones <drjo...@redhat.com> > > Question: For testing, did you dump all the ID registers on this > model and compare them with a dump of ID registers from real > hardware? If so, that would be good info to put in the commit > message or at least the cover letter. > > Thanks, > drew