On 8/30/21 7:16 PM, Frédéric Pétrot wrote:
> Adding the support for the 128-bit arithmetic and logic instructions.
> Remember that all (i) instructions are now acting on 128-bit registers, that
> a few others are added to cope with values that are held on 64 bits within
> the 128-bit registers, and that the ones that cope with values on 32-bit
> must also be modified for proper sign extension.
> Most algorithms taken from Hackers' delight.
>
> Signed-off-by: Frédéric Pétrot <[email protected]>
> Co-authored-by: Fabien Portas <[email protected]>
> ---
> target/riscv/insn32.decode | 13 +
> target/riscv/insn_trans/trans_rvi.c.inc | 955 +++++++++++++++++++++++-
> target/riscv/translate.c | 25 +
> 3 files changed, 976 insertions(+), 17 deletions(-)
> diff --git a/target/riscv/insn_trans/trans_rvi.c.inc
> b/target/riscv/insn_trans/trans_rvi.c.inc
> index 772330a766..0401ba3d69 100644
> --- a/target/riscv/insn_trans/trans_rvi.c.inc
> +++ b/target/riscv/insn_trans/trans_rvi.c.inc
> @@ -26,14 +26,20 @@ static bool trans_illegal(DisasContext *ctx, arg_empty *a)
>
> static bool trans_c64_illegal(DisasContext *ctx, arg_empty *a)
> {
> - REQUIRE_64BIT(ctx);
> - return trans_illegal(ctx, a);
> + REQUIRE_64_OR_128BIT(ctx);
> + return trans_illegal(ctx, a);
> }
>
> static bool trans_lui(DisasContext *ctx, arg_lui *a)
> {
> if (a->rd != 0) {
> tcg_gen_movi_tl(cpu_gpr[a->rd], a->imm);
> +#if defined(TARGET_RISCV128)
> + if (is_128bit(ctx)) {
Maybe this could allow the compiler eventually elide the
code and avoid superfluous #ifdef'ry:
if (TARGET_LONG_BITS >= 128) {
> + tcg_gen_ext_i64_i128(cpu_gpr[a->rd], cpu_gprh[a->rd],
> + cpu_gpr[a->rd]);
> + }
> +#endif
> }
> return true;
> }
