> On Aug 31, 2021, at 11:34 PM, Cédric Le Goater <c...@kaod.org> wrote:
>
> Adding Peter Maydell and Joel.
>
> On 9/1/21 1:31 AM, p...@fb.com wrote:
>> From: Peter Delevoryas <p...@fb.com>
>>
>> When you run QEMU with an Aspeed machine and a single serial device
>> using stdio like this:
>>
>> qemu -machine ast2600-evb -drive ... -serial stdio
>>
>> The guest OS can read and write to the UART5 registers at 0x1E784000 and
>> it will receive from stdin and write to stdout. The Aspeed SoC's have a
>> lot more UART's though (AST2500 has 5, AST2600 has 13) and depending on
>> the board design, may be using any of them as the serial console. (See
>> "stdout-path" in a DTS to check which one is chosen).
>>
>> Most boards, including all of those currently defined in
>> hw/arm/aspeed.c, just use UART5, but some use UART1. This change adds
>> some flexibility for different boards without requiring users to change
>> their command-line invocation of QEMU.
>>
>> I tested this doesn't break existing code by booting an AST2500 OpenBMC
>> image and an AST2600 OpenBMC image, each using UART5 as the console.
>>
>> Then I tested switching the default to UART1 and booting an AST2600
>> OpenBMC image that uses UART1, and that worked too.
>>
>> Signed-off-by: Peter Delevoryas <p...@fb.com>
>
> Some comments below,
>
>> ---
>> hw/arm/aspeed.c | 1 +
>> hw/arm/aspeed_ast2600.c | 11 +++++++----
>> hw/arm/aspeed_soc.c | 9 ++++++---
>> include/hw/arm/aspeed.h | 1 +
>> 4 files changed, 15 insertions(+), 7 deletions(-)
>>
>> diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
>> index 9d43e26c51..74379907ff 100644
>> --- a/hw/arm/aspeed.c
>> +++ b/hw/arm/aspeed.c
>> @@ -804,6 +804,7 @@ static void aspeed_machine_class_init(ObjectClass *oc,
>> void *data)
>> mc->no_parallel = 1;
>> mc->default_ram_id = "ram";
>> amc->macs_mask = ASPEED_MAC0_ON;
>> + amc->serial_hd0 = ASPEED_DEV_UART5;
>>
>> aspeed_machine_class_props_init(oc);
>> }
>> diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c
>> index e3013128c6..361a456214 100644
>> --- a/hw/arm/aspeed_ast2600.c
>> +++ b/hw/arm/aspeed_ast2600.c
>> @@ -10,6 +10,7 @@
>> #include "qemu/osdep.h"
>> #include "qapi/error.h"
>> #include "hw/misc/unimp.h"
>> +#include "hw/arm/aspeed.h"
>> #include "hw/arm/aspeed_soc.h"
>> #include "hw/char/serial.h"
>> #include "qemu/module.h"
>> @@ -231,6 +232,8 @@ static uint64_t aspeed_calc_affinity(int cpu)
>> static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
>> {
>> int i;
>> + AspeedMachineState *bmc = ASPEED_MACHINE(qdev_get_machine());
>> + AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(bmc);
>
> This is reaching into the machine from the SoC which is not good
> practice.
>
> What you should do is add an attribute in AspeedSoCState and a
> property in aspeed_soc_properties[]. This property would be set
> in aspeed_machine_init() before realizing the soc object. Look
> at "dram" for an example.
Ohhhh I see, thanks for explaining, I’ll fix this.
>
> Then, in the aspeed_soc_*_realize routines, you would use the
> attribute to initialize the default serial device.
>
> I don't really know what to call this attribute and property.
> How about uart_default and "uart-default" ?
Oh ok, yeah I’ll change it to uart_default and “uart-default”.
>
> Thanks,
>
> C.
>
>> AspeedSoCState *s = ASPEED_SOC(dev);
>> AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
>> Error *err = NULL;
>> @@ -322,10 +325,10 @@ static void aspeed_soc_ast2600_realize(DeviceState
>> *dev, Error **errp)
>> sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq);
>> }
>>
>> - /* UART - attach an 8250 to the IO space as our UART5 */
>> - serial_mm_init(get_system_memory(), sc->memmap[ASPEED_DEV_UART5], 2,
>> - aspeed_soc_get_irq(s, ASPEED_DEV_UART5),
>> - 38400, serial_hd(0), DEVICE_LITTLE_ENDIAN);
>> + /* Wire up the first serial device, usually either UART5 or UART1 */
>> + serial_mm_init(get_system_memory(), sc->memmap[amc->serial_hd0], 2,
>> + aspeed_soc_get_irq(s, amc->serial_hd0), 38400,
>> + serial_hd(0), DEVICE_LITTLE_ENDIAN);
>>
>> /* I2C */
>> object_property_set_link(OBJECT(&s->i2c), "dram", OBJECT(s->dram_mr),
>> diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c
>> index 3ad6c56fa9..77422bbeb1 100644
>> --- a/hw/arm/aspeed_soc.c
>> +++ b/hw/arm/aspeed_soc.c
>> @@ -13,6 +13,7 @@
>> #include "qemu/osdep.h"
>> #include "qapi/error.h"
>> #include "hw/misc/unimp.h"
>> +#include "hw/arm/aspeed.h"
>> #include "hw/arm/aspeed_soc.h"
>> #include "hw/char/serial.h"
>> #include "qemu/module.h"
>> @@ -221,6 +222,8 @@ static void aspeed_soc_init(Object *obj)
>> static void aspeed_soc_realize(DeviceState *dev, Error **errp)
>> {
>> int i;
>> + AspeedMachineState *bmc = ASPEED_MACHINE(qdev_get_machine());
>> + AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(bmc);
>> AspeedSoCState *s = ASPEED_SOC(dev);
>> AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
>> Error *err = NULL;
>> @@ -287,9 +290,9 @@ static void aspeed_soc_realize(DeviceState *dev, Error
>> **errp)
>> sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq);
>> }
>>
>> - /* UART - attach an 8250 to the IO space as our UART5 */
>> - serial_mm_init(get_system_memory(), sc->memmap[ASPEED_DEV_UART5], 2,
>> - aspeed_soc_get_irq(s, ASPEED_DEV_UART5), 38400,
>> + /* Wire up the first serial device, usually either UART5 or UART1 */
>> + serial_mm_init(get_system_memory(), sc->memmap[amc->serial_hd0], 2,
>> + aspeed_soc_get_irq(s, amc->serial_hd0), 38400,
>> serial_hd(0), DEVICE_LITTLE_ENDIAN);
>>
>> /* I2C */
>> diff --git a/include/hw/arm/aspeed.h b/include/hw/arm/aspeed.h
>> index c9747b15fc..bc0f27885a 100644
>> --- a/include/hw/arm/aspeed.h
>> +++ b/include/hw/arm/aspeed.h
>> @@ -38,6 +38,7 @@ struct AspeedMachineClass {
>> uint32_t num_cs;
>> uint32_t macs_mask;
>> void (*i2c_init)(AspeedMachineState *bmc);
>> + uint32_t serial_hd0;
>> };
