On 9/2/21 2:40 PM, Song Gao wrote:
+#define FCSR0_M1 0x1f /* FCSR1 mask, Enables */ +#define FCSR0_M2 0x1f1f0000 /* FCSR2 mask, Cause and Flags */ +#define FCSR0_M3 0x300 /* FCSR3 mask, Round Mode */ +#define FCSR0_RM 8 /* Round Mode bit num on fcsr0 */ +#define GET_FP_CAUSE(reg) (((reg) >> 24) & 0x1f) +#define GET_FP_ENABLE(reg) (reg & 0x1f) +#define GET_FP_FLAGS(reg) (((reg) >> 16) & 0x1f) +#define SET_FP_CAUSE(reg, v) do { (reg) = ((reg) & ~(0x1f << 24)) | \ + ((v & 0x1f) << 24); \ + } while (0) +#define SET_FP_ENABLE(reg, v) do { (reg) = ((reg) & ~(0x1f) | (v & 0x1f); \ + } while (0) +#define SET_FP_FLAGS(reg, v) do { (reg) = ((reg) & ~(0x1f << 16)) | \ + ((v & 0x1f) << 16); \ + } while (0) +#define UPDATE_FP_FLAGS(reg, v) do { (reg) |= ((v & 0x1f) << 16); } while (0)
Better to use "hw/registerfields.h": FIELD(FCSR, ENABLES, 0, 5) FIELD(FCSR, RM, 8, 2) FIELD(FCSR, FLAGS, 16, 5) FIELD(FCSR, CAUSE, 24, 5) Then e.g. #define GET_FP_CAUSE(REG) FIELD_EX32(REG, FCSR, CAUSE) #define SET_FP_CAUSE(REG, V) FIELD_DP32(REG, FCSR, CAUSE, V) #define UPDATE_FP_FLAGS(REG, V) \ do { (REG) |= FIELD_DP32(0, FCSR, FLAGS, V); } while (0)
+static inline void cpu_get_tb_cpu_state(CPULoongArchState *env, + target_ulong *pc, + target_ulong *cs_base, + uint32_t *flags) +{ + *pc = env->pc; + *cs_base = 0; +}
Missing *flags = 0. r~