On Fri, Sep 03, 2021 at 05:31:02PM -0300, Daniel Henrique Barboza wrote: > From: Gustavo Romero <grom...@linux.ibm.com> > > We're going to add PMU support for TCG PPC64 chips, based on IBM POWER8+ > emulation and following PowerISA v3.1. > > Let's start by handling the user read of UMMCR0 and UMMCR2. According to > PowerISA 3.1 these registers omit some of its bits from userspace. > > CC: Gustavo Romero <gustavo.rom...@linaro.org> > Signed-off-by: Gustavo Romero <grom...@linux.ibm.com> > Signed-off-by: Daniel Henrique Barboza <danielhb...@gmail.com>
LGTM except for one nit... [snip] > +void spr_read_MMCR2_ureg(DisasContext *ctx, int gprn, int sprn) > +{ > + TCGv t0 = tcg_temp_new(); > + > + /* > + * On read, filter out all bits that are not FCnP0 bits. > + * When MMCR0[PMCC] is set to 0b10 or 0b11, providing > + * problem state programs read/write access to MMCR2, > + * only the FCnP0 bits can be accessed. All other bits are > + * not changed when mtspr is executed in problem state, and > + * all other bits return 0s when mfspr is executed in problem > + * state, according to ISA v3.1, section 10.4.6 Monitor Mode > + * Control Register 2, p. 1316, third paragraph. > + */ > + gen_load_spr(t0, SPR_POWER_MMCR2); > + tcg_gen_andi_tl(t0, t0, 0x4020100804020000UL); A #define for this mask... and #defines with meaningful names for the various bits it includes would be nice. > + tcg_gen_mov_tl(cpu_gpr[gprn], t0); > + > + tcg_temp_free(t0); > +} > + > #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) > void spr_write_ureg(DisasContext *ctx, int sprn, int gprn) > { -- David Gibson | I'll have my music baroque, and my code david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_ | _way_ _around_! http://www.ozlabs.org/~dgibson
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