On Thu, 2 Sept 2021 at 06:40, Edgar E. Iglesias <edgar.igles...@xilinx.com> wrote: > > On Wed, Sep 01, 2021 at 08:45:15PM +0800, Bin Meng wrote: > > As of today, when booting upstream U-Boot for Xilinx Zynq, the UART > > does not receive anything. Debugging shows that the UART input clock > > frequency is zero which prevents the UART from receiving anything as. > > per the logic in uart_receive(). > > > > Note the U-Boot can still output data to the UART tx fifo, which should > > not happen, as the design seems to prevent the data transmission when > > clock is not enabled but somehow it only applies to the Rx side. > > > > For anyone who is interested to give a try, here is the U-Boot defconfig: > > $ make xilinx_zynq_virt_defconfig > > > > and QEMU commands to test U-Boot: > > $ qemu-system-arm -M xilinx-zynq-a9 -m 1G -display none -serial null > > -serial stdio \ > > -device loader,file=u-boot-dtb.bin,addr=0x4000000,cpu-num=0 > > > > Note U-Boot used to boot properly in QEMU 4.2.0 which is the QEMU > > version used in current U-Boot's CI testing. The UART clock changes > > were introduced by the following 3 commits: > > > > 38867cb7ec90 ("hw/misc/zynq_slcr: add clock generation for uarts") > > b636db306e06 ("hw/char/cadence_uart: add clock support") > > 5b49a34c6800 ("hw/arm/xilinx_zynq: connect uart clocks to slcr") > > Thanks Bin, > > On the entire series: > > Reviewed-by: Edgar E. Iglesias <edgar.igles...@xilinx.com>
Applied to target-arm.next, thanks. -- PMM