On Wed, Sep 15, 2021 at 6:47 PM Bin Meng <bmeng...@gmail.com> wrote:
>
> The macro name HCOUNTEREN_CY suggests it is for CSR HCOUNTEREN, but
> in fact it applies to M-mode and S-mode CSR too. Rename these macros
> to have the COUNTEREN_ prefix.
>
> Signed-off-by: Bin Meng <bmeng...@gmail.com>
Thanks!
Applied to riscv-to-apply.next
Alistair
> ---
>
> target/riscv/cpu_bits.h | 8 ++++----
> target/riscv/csr.c | 24 ++++++++++++------------
> 2 files changed, 16 insertions(+), 16 deletions(-)
>
> diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
> index 7330ff5a19..34564d367c 100644
> --- a/target/riscv/cpu_bits.h
> +++ b/target/riscv/cpu_bits.h
> @@ -397,10 +397,10 @@
> #define HSTATUS32_WPRI 0xFF8FF87E
> #define HSTATUS64_WPRI 0xFFFFFFFFFF8FF87EULL
>
> -#define HCOUNTEREN_CY (1 << 0)
> -#define HCOUNTEREN_TM (1 << 1)
> -#define HCOUNTEREN_IR (1 << 2)
> -#define HCOUNTEREN_HPM3 (1 << 3)
> +#define COUNTEREN_CY (1 << 0)
> +#define COUNTEREN_TM (1 << 1)
> +#define COUNTEREN_IR (1 << 2)
> +#define COUNTEREN_HPM3 (1 << 3)
>
> /* Privilege modes */
> #define PRV_U 0
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 50a2c3a3b4..1cd34a6453 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -71,20 +71,20 @@ static RISCVException ctr(CPURISCVState *env, int csrno)
> if (riscv_cpu_virt_enabled(env)) {
> switch (csrno) {
> case CSR_CYCLE:
> - if (!get_field(env->hcounteren, HCOUNTEREN_CY) &&
> - get_field(env->mcounteren, HCOUNTEREN_CY)) {
> + if (!get_field(env->hcounteren, COUNTEREN_CY) &&
> + get_field(env->mcounteren, COUNTEREN_CY)) {
> return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
> }
> break;
> case CSR_TIME:
> - if (!get_field(env->hcounteren, HCOUNTEREN_TM) &&
> - get_field(env->mcounteren, HCOUNTEREN_TM)) {
> + if (!get_field(env->hcounteren, COUNTEREN_TM) &&
> + get_field(env->mcounteren, COUNTEREN_TM)) {
> return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
> }
> break;
> case CSR_INSTRET:
> - if (!get_field(env->hcounteren, HCOUNTEREN_IR) &&
> - get_field(env->mcounteren, HCOUNTEREN_IR)) {
> + if (!get_field(env->hcounteren, COUNTEREN_IR) &&
> + get_field(env->mcounteren, COUNTEREN_IR)) {
> return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
> }
> break;
> @@ -98,20 +98,20 @@ static RISCVException ctr(CPURISCVState *env, int csrno)
> if (riscv_cpu_is_32bit(env)) {
> switch (csrno) {
> case CSR_CYCLEH:
> - if (!get_field(env->hcounteren, HCOUNTEREN_CY) &&
> - get_field(env->mcounteren, HCOUNTEREN_CY)) {
> + if (!get_field(env->hcounteren, COUNTEREN_CY) &&
> + get_field(env->mcounteren, COUNTEREN_CY)) {
> return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
> }
> break;
> case CSR_TIMEH:
> - if (!get_field(env->hcounteren, HCOUNTEREN_TM) &&
> - get_field(env->mcounteren, HCOUNTEREN_TM)) {
> + if (!get_field(env->hcounteren, COUNTEREN_TM) &&
> + get_field(env->mcounteren, COUNTEREN_TM)) {
> return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
> }
> break;
> case CSR_INSTRETH:
> - if (!get_field(env->hcounteren, HCOUNTEREN_IR) &&
> - get_field(env->mcounteren, HCOUNTEREN_IR)) {
> + if (!get_field(env->hcounteren, COUNTEREN_IR) &&
> + get_field(env->mcounteren, COUNTEREN_IR)) {
> return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
> }
> break;
> --
> 2.25.1
>
>
