Cache options must be enabled for the cores that have cache to avoid
illegal instruction exceptions.
Signed-off-by: Max Filippov <jcmvb...@gmail.com>
---
target-xtensa/overlay_tool.h | 6 ++++++
1 files changed, 6 insertions(+), 0 deletions(-)
diff --git a/target-xtensa/overlay_tool.h b/target-xtensa/overlay_tool.h
index 060e8e5..9cef27d 100644
--- a/target-xtensa/overlay_tool.h
+++ b/target-xtensa/overlay_tool.h
@@ -71,6 +71,12 @@
XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT) | \
XCHAL_OPTION(XCHAL_HAVE_CCOUNT, XTENSA_OPTION_TIMER_INTERRUPT) | \
/* Local memory, TODO */ \
+ XCHAL_OPTION(XCHAL_ICACHE_WAYS, XTENSA_OPTION_ICACHE) | \
+ XCHAL_OPTION(XCHAL_ICACHE_LINE_LOCKABLE, \
+ XTENSA_OPTION_ICACHE_INDEX_LOCK) | \
+ XCHAL_OPTION(XCHAL_DCACHE_WAYS, XTENSA_OPTION_DCACHE) | \
+ XCHAL_OPTION(XCHAL_DCACHE_LINE_LOCKABLE, \
+ XTENSA_OPTION_DCACHE_INDEX_LOCK) | \
XCHAL_OPTION(XCHAL_UNALIGNED_LOAD_HW, XTENSA_OPTION_HW_ALIGNMENT) | \
/* Memory protection and translation */ \
XCHAL_OPTION(XCHAL_HAVE_MIMIC_CACHEATTR, \
--
1.7.6.4
