Convert 3-register floating-point or fixed-point operations
to decodetree.
Signed-off-by: Philippe Mathieu-Daudé <f4...@amsat.org>
---
target/mips/tcg/msa.decode | 8 ++++
target/mips/tcg/msa_translate.c | 70 +++++++++++++++------------------
2 files changed, 39 insertions(+), 39 deletions(-)
diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode
index 72447041fef..5c6a7415271 100644
--- a/target/mips/tcg/msa.decode
+++ b/target/mips/tcg/msa.decode
@@ -24,6 +24,7 @@
@vec ...... ..... wt:5 ws:5 wd:5 ...... &msa_r df=0
@2r ...... ........ df:2 ws:5 wd:5 ...... &msa_r wt=0
@2rf ...... ......... df:1 ws:5 wd:5 ...... &msa_r wt=0
+@3rf ...... .... df:1 wt:5 ws:5 wd:5 ...... &msa_r
@u5 ...... ... df:2 sa:5 ws:5 wd:5 ...... &msa_ldst
@s5 ...... ... df:2 sa:s5 ws:5 wd:5 ...... &msa_ldst
@ldi ...... ... df:2 sa:s10 wd:5 ...... &msa_ldst ws=0
@@ -78,6 +79,13 @@ BNZ 010001 111 .. ..... ................
@bz
SRARI 011110 010 ....... ..... ..... 001010 @bit
SRLRI 011110 011 ....... ..... ..... 001010 @bit
+ MUL_Q 011110 0100 . ..... ..... ..... 011100 @3rf
+ MADD_Q 011110 0101 . ..... ..... ..... 011100 @3rf
+ MSUB_Q 011110 0110 . ..... ..... ..... 011100 @3rf
+ MULR_Q 011110 1100 . ..... ..... ..... 011100 @3rf
+ MADDR_Q 011110 1101 . ..... ..... ..... 011100 @3rf
+ MSUBR_Q 011110 1110 . ..... ..... ..... 011100 @3rf
+
AND_V 011110 00000 ..... ..... ..... 011110 @vec
OR_V 011110 00001 ..... ..... ..... 011110 @vec
NOR_V 011110 00010 ..... ..... ..... 011110 @vec
diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c
index 461a427c9df..6e50bc9edf4 100644
--- a/target/mips/tcg/msa_translate.c
+++ b/target/mips/tcg/msa_translate.c
@@ -130,12 +130,9 @@ enum {
OPC_FCNE_df = (0x3 << 22) | OPC_MSA_3RF_1C,
OPC_FCLT_df = (0x4 << 22) | OPC_MSA_3RF_1A,
OPC_FMADD_df = (0x4 << 22) | OPC_MSA_3RF_1B,
- OPC_MUL_Q_df = (0x4 << 22) | OPC_MSA_3RF_1C,
OPC_FCULT_df = (0x5 << 22) | OPC_MSA_3RF_1A,
OPC_FMSUB_df = (0x5 << 22) | OPC_MSA_3RF_1B,
- OPC_MADD_Q_df = (0x5 << 22) | OPC_MSA_3RF_1C,
OPC_FCLE_df = (0x6 << 22) | OPC_MSA_3RF_1A,
- OPC_MSUB_Q_df = (0x6 << 22) | OPC_MSA_3RF_1C,
OPC_FCULE_df = (0x7 << 22) | OPC_MSA_3RF_1A,
OPC_FEXP2_df = (0x7 << 22) | OPC_MSA_3RF_1B,
OPC_FSAF_df = (0x8 << 22) | OPC_MSA_3RF_1A,
@@ -149,13 +146,10 @@ enum {
OPC_FSNE_df = (0xB << 22) | OPC_MSA_3RF_1C,
OPC_FSLT_df = (0xC << 22) | OPC_MSA_3RF_1A,
OPC_FMIN_df = (0xC << 22) | OPC_MSA_3RF_1B,
- OPC_MULR_Q_df = (0xC << 22) | OPC_MSA_3RF_1C,
OPC_FSULT_df = (0xD << 22) | OPC_MSA_3RF_1A,
OPC_FMIN_A_df = (0xD << 22) | OPC_MSA_3RF_1B,
- OPC_MADDR_Q_df = (0xD << 22) | OPC_MSA_3RF_1C,
OPC_FSLE_df = (0xE << 22) | OPC_MSA_3RF_1A,
OPC_FMAX_df = (0xE << 22) | OPC_MSA_3RF_1B,
- OPC_MSUBR_Q_df = (0xE << 22) | OPC_MSA_3RF_1C,
OPC_FSULE_df = (0xF << 22) | OPC_MSA_3RF_1A,
OPC_FMAX_A_df = (0xF << 22) | OPC_MSA_3RF_1B,
};
@@ -251,6 +245,9 @@ static inline bool check_msa_access(DisasContext *ctx)
#define TRANS_MSA(NAME, trans_func, gen_func) \
TRANS_CHECK(NAME, check_msa_access(ctx), trans_func, gen_func)
+#define TRANS_DF(NAME, trans_func, df, gen_func) \
+ TRANS_CHECK(NAME, check_msa_access(ctx), trans_func, df, gen_func)
+
#define TRANS_DF_E(NAME, trans_func, gen_func) \
TRANS_CHECK(NAME, check_msa_access(ctx), trans_func, \
gen_func##_b, gen_func##_h, gen_func##_w, gen_func##_d)
@@ -1652,6 +1649,33 @@ static void gen_msa_elm(DisasContext *ctx)
gen_msa_elm_df(ctx, df, n);
}
+static bool trans_msa_3rf(DisasContext *ctx, arg_msa_r *a,
+ enum CPUMIPSMSADataFormat df_base,
+ void (*gen_msa_3rf)(TCGv_ptr, TCGv_i32, TCGv_i32,
+ TCGv_i32, TCGv_i32))
+{
+ TCGv_i32 twd = tcg_const_i32(a->wd);
+ TCGv_i32 tws = tcg_const_i32(a->ws);
+ TCGv_i32 twt = tcg_const_i32(a->wt);
+ /* adjust df value for floating-point instruction */
+ TCGv_i32 tdf = tcg_constant_i32(a->df + df_base);
+
+ gen_msa_3rf(cpu_env, tdf, twd, tws, twt);
+
+ tcg_temp_free_i32(twt);
+ tcg_temp_free_i32(tws);
+ tcg_temp_free_i32(twd);
+
+ return true;
+}
+
+TRANS_DF(MUL_Q, trans_msa_3rf, DF_HALF, gen_helper_msa_mul_q_df);
+TRANS_DF(MADD_Q, trans_msa_3rf, DF_HALF, gen_helper_msa_madd_q_df);
+TRANS_DF(MSUB_Q, trans_msa_3rf, DF_HALF, gen_helper_msa_msub_q_df);
+TRANS_DF(MULR_Q, trans_msa_3rf, DF_HALF, gen_helper_msa_mulr_q_df);
+TRANS_DF(MADDR_Q, trans_msa_3rf, DF_HALF, gen_helper_msa_maddr_q_df);
+TRANS_DF(MSUBR_Q, trans_msa_3rf, DF_HALF, gen_helper_msa_msubr_q_df);
+
static void gen_msa_3rf(DisasContext *ctx)
{
#define MASK_MSA_3RF(op) (MASK_MSA_MINOR(op) | (op & (0xf << 22)))
@@ -1663,22 +1687,8 @@ static void gen_msa_3rf(DisasContext *ctx)
TCGv_i32 twd = tcg_const_i32(wd);
TCGv_i32 tws = tcg_const_i32(ws);
TCGv_i32 twt = tcg_const_i32(wt);
- TCGv_i32 tdf;
-
/* adjust df value for floating-point instruction */
- switch (MASK_MSA_3RF(ctx->opcode)) {
- case OPC_MUL_Q_df:
- case OPC_MADD_Q_df:
- case OPC_MSUB_Q_df:
- case OPC_MULR_Q_df:
- case OPC_MADDR_Q_df:
- case OPC_MSUBR_Q_df:
- tdf = tcg_constant_i32(DF_HALF + df);
- break;
- default:
- tdf = tcg_constant_i32(DF_WORD + df);
- break;
- }
+ TCGv_i32 tdf = tcg_constant_i32(DF_WORD + df);
switch (MASK_MSA_3RF(ctx->opcode)) {
case OPC_FCAF_df:
@@ -1720,24 +1730,15 @@ static void gen_msa_3rf(DisasContext *ctx)
case OPC_FMADD_df:
gen_helper_msa_fmadd_df(cpu_env, tdf, twd, tws, twt);
break;
- case OPC_MUL_Q_df:
- gen_helper_msa_mul_q_df(cpu_env, tdf, twd, tws, twt);
- break;
case OPC_FCULT_df:
gen_helper_msa_fcult_df(cpu_env, tdf, twd, tws, twt);
break;
case OPC_FMSUB_df:
gen_helper_msa_fmsub_df(cpu_env, tdf, twd, tws, twt);
break;
- case OPC_MADD_Q_df:
- gen_helper_msa_madd_q_df(cpu_env, tdf, twd, tws, twt);
- break;
case OPC_FCLE_df:
gen_helper_msa_fcle_df(cpu_env, tdf, twd, tws, twt);
break;
- case OPC_MSUB_Q_df:
- gen_helper_msa_msub_q_df(cpu_env, tdf, twd, tws, twt);
- break;
case OPC_FCULE_df:
gen_helper_msa_fcule_df(cpu_env, tdf, twd, tws, twt);
break;
@@ -1777,27 +1778,18 @@ static void gen_msa_3rf(DisasContext *ctx)
case OPC_FMIN_df:
gen_helper_msa_fmin_df(cpu_env, tdf, twd, tws, twt);
break;
- case OPC_MULR_Q_df:
- gen_helper_msa_mulr_q_df(cpu_env, tdf, twd, tws, twt);
- break;
case OPC_FSULT_df:
gen_helper_msa_fsult_df(cpu_env, tdf, twd, tws, twt);
break;
case OPC_FMIN_A_df:
gen_helper_msa_fmin_a_df(cpu_env, tdf, twd, tws, twt);
break;
- case OPC_MADDR_Q_df:
- gen_helper_msa_maddr_q_df(cpu_env, tdf, twd, tws, twt);
- break;
case OPC_FSLE_df:
gen_helper_msa_fsle_df(cpu_env, tdf, twd, tws, twt);
break;
case OPC_FMAX_df:
gen_helper_msa_fmax_df(cpu_env, tdf, twd, tws, twt);
break;
- case OPC_MSUBR_Q_df:
- gen_helper_msa_msubr_q_df(cpu_env, tdf, twd, tws, twt);
- break;
case OPC_FSULE_df:
gen_helper_msa_fsule_df(cpu_env, tdf, twd, tws, twt);
break;
--
2.31.1
