Convert the COPY_S (Element Copy to GPR Signed) opcode
and INSERT (GPR Insert Element) opcode to decodetree.
Signed-off-by: Philippe Mathieu-Daudé <f4...@amsat.org>
---
target/mips/tcg/msa.decode | 2 +
target/mips/tcg/msa_translate.c | 92 ++++-----------------------------
2 files changed, 12 insertions(+), 82 deletions(-)
diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode
index 80a06d12746..dc5e561b9dc 100644
--- a/target/mips/tcg/msa.decode
+++ b/target/mips/tcg/msa.decode
@@ -156,7 +156,9 @@ BNZ 010001 111 .. ..... ................
@bz
SLDI 011110 0000 ...... ..... ..... 011001 @elm_df
SPLATI 011110 0001 ...... ..... ..... 011001 @elm_df
+ COPY_S 011110 0010 ...... ..... ..... 011001 @elm_df
COPY_U 011110 0011 ...... ..... ..... 011001 @elm_df
+ INSERT 011110 0100 ...... ..... ..... 011001 @elm_df
INSVE 011110 0101 ...... ..... ..... 011001 @elm_df
FCAF 011110 0000 . ..... ..... ..... 011010 @3rf
diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c
index e033b365fdd..ff5dbd99f84 100644
--- a/target/mips/tcg/msa_translate.c
+++ b/target/mips/tcg/msa_translate.c
@@ -31,9 +31,7 @@ enum {
/* ELM instructions df(bits 21..16) = _b, _h, _w, _d */
OPC_CTCMSA = (0x0 << 22) | (0x3E << 16) | OPC_MSA_ELM,
OPC_CFCMSA = (0x1 << 22) | (0x3E << 16) | OPC_MSA_ELM,
- OPC_COPY_S_df = (0x2 << 22) | (0x00 << 16) | OPC_MSA_ELM,
OPC_MOVE_V = (0x2 << 22) | (0x3E << 16) | OPC_MSA_ELM,
- OPC_INSERT_df = (0x4 << 22) | (0x00 << 16) | OPC_MSA_ELM,
};
static const char msaregnames[][6] = {
@@ -138,6 +136,11 @@ static inline bool check_msa_access(DisasContext *ctx)
TRANS_CHECK(NAME, check_msa_access(ctx), trans_func, \
NULL, gen_func##_h, gen_func##_w, gen_func##_d)
+#define TRANS_DF_D64(NAME, trans_func, gen_func) \
+ TRANS_CHECK(NAME, check_msa_access(ctx), trans_func, \
+ DF_WORD, DF_DOUBLE, \
+ gen_func##_b, gen_func##_h, gen_func##_w, gen_func##_d)
+
#define TRANS_DF_W64(NAME, trans_func, gen_func) \
TRANS_CHECK(NAME, check_msa_access(ctx), trans_func, \
DF_HALF, DF_WORD, \
@@ -642,7 +645,8 @@ static bool trans_msa_elm_d64(DisasContext *ctx,
arg_msa_elm *a,
gen_msa_elm_w(cpu_env, twd, tws, tn);
break;
case DF_DOUBLE:
- g_assert_not_reached();
+ assert(gen_msa_elm_d != NULL);
+ gen_msa_elm_d(cpu_env, twd, tws, tn);
break;
}
@@ -652,97 +656,21 @@ static bool trans_msa_elm_d64(DisasContext *ctx,
arg_msa_elm *a,
return true;
}
+TRANS_DF_D64(COPY_S, trans_msa_elm_d64, gen_helper_msa_copy_s);
TRANS_DF_W64(COPY_U, trans_msa_elm_d64, gen_helper_msa_copy_u);
-
-static void gen_msa_elm_df(DisasContext *ctx, uint32_t df, uint32_t n)
-{
-#define MASK_MSA_ELM(op) (MASK_MSA_MINOR(op) | (op & (0xf << 22)))
- uint8_t ws = (ctx->opcode >> 11) & 0x1f;
- uint8_t wd = (ctx->opcode >> 6) & 0x1f;
-
- TCGv_i32 tws = tcg_const_i32(ws);
- TCGv_i32 twd = tcg_const_i32(wd);
- TCGv_i32 tn = tcg_const_i32(n);
-
- switch (MASK_MSA_ELM(ctx->opcode)) {
- case OPC_COPY_S_df:
- case OPC_INSERT_df:
-#if !defined(TARGET_MIPS64)
- /* Double format valid only for MIPS64 */
- if (df == DF_DOUBLE) {
- gen_reserved_instruction(ctx);
- break;
- }
-#endif
- switch (MASK_MSA_ELM(ctx->opcode)) {
- case OPC_COPY_S_df:
- if (likely(wd != 0)) {
- switch (df) {
- case DF_BYTE:
- gen_helper_msa_copy_s_b(cpu_env, twd, tws, tn);
- break;
- case DF_HALF:
- gen_helper_msa_copy_s_h(cpu_env, twd, tws, tn);
- break;
- case DF_WORD:
- gen_helper_msa_copy_s_w(cpu_env, twd, tws, tn);
- break;
-#if defined(TARGET_MIPS64)
- case DF_DOUBLE:
- gen_helper_msa_copy_s_d(cpu_env, twd, tws, tn);
- break;
-#endif
- default:
- assert(0);
- }
- }
- break;
- case OPC_INSERT_df:
- switch (df) {
- case DF_BYTE:
- gen_helper_msa_insert_b(cpu_env, twd, tws, tn);
- break;
- case DF_HALF:
- gen_helper_msa_insert_h(cpu_env, twd, tws, tn);
- break;
- case DF_WORD:
- gen_helper_msa_insert_w(cpu_env, twd, tws, tn);
- break;
-#if defined(TARGET_MIPS64)
- case DF_DOUBLE:
- gen_helper_msa_insert_d(cpu_env, twd, tws, tn);
- break;
-#endif
- default:
- assert(0);
- }
- break;
- }
- break;
- default:
- MIPS_INVAL("MSA instruction");
- gen_reserved_instruction(ctx);
- }
- tcg_temp_free_i32(twd);
- tcg_temp_free_i32(tws);
- tcg_temp_free_i32(tn);
-}
+TRANS_DF_D64(INSERT, trans_msa_elm_d64, gen_helper_msa_insert);
static void gen_msa_elm(DisasContext *ctx)
{
uint8_t dfn = (ctx->opcode >> 16) & 0x3f;
- uint32_t df, n;
if (dfn == 0x3E) {
/* CTCMSA, CFCMSA, MOVE.V */
gen_msa_elm_3e(ctx);
return;
- } else if (!df_extract(df_elm, dfn, &df, &n)) {
- gen_reserved_instruction(ctx);
- return;
}
- gen_msa_elm_df(ctx, df, n);
+ gen_reserved_instruction(ctx);
}
static bool trans_msa_3rf(DisasContext *ctx, arg_msa_r *a,
--
2.31.1
