Implement the following PowerISA v3.1 instruction:
dcffixqq: DFP Convert From Fixed Quadword Quad
Signed-off-by: Luis Pires <luis.pi...@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
---
target/ppc/dfp_helper.c | 12 ++++++++++++
target/ppc/helper.h | 1 +
target/ppc/insn32.decode | 8 ++++++++
target/ppc/translate.c | 5 +++++
target/ppc/translate/dfp-impl.c.inc | 17 +++++++++++++++++
5 files changed, 43 insertions(+)
diff --git a/target/ppc/dfp_helper.c b/target/ppc/dfp_helper.c
index 07341a69f5..6b837c4450 100644
--- a/target/ppc/dfp_helper.c
+++ b/target/ppc/dfp_helper.c
@@ -970,6 +970,18 @@ static void CFFIX_PPs(struct PPC_DFP *dfp)
DFP_HELPER_CFFIX(dcffix, 64)
DFP_HELPER_CFFIX(dcffixq, 128)
+void helper_DCFFIXQQ(CPUPPCState *env, ppc_fprp_t *t, ppc_avr_t *b)
+{
+ struct PPC_DFP dfp;
+
+ dfp_prepare_decimal128(&dfp, NULL, NULL, env);
+ decNumberFromInt128(&dfp.t, (uint64_t)b->VsrD(1), (int64_t)b->VsrD(0));
+ dfp_finalize_decimal128(&dfp);
+ CFFIX_PPs(&dfp);
+
+ set_dfp128(t, &dfp.vt);
+}
+
#define DFP_HELPER_CTFIX(op, size) \
void helper_##op(CPUPPCState *env, ppc_fprp_t *t, ppc_fprp_t *b) \
{ \
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 4076aa281e..fff7bd46ad 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -734,6 +734,7 @@ DEF_HELPER_3(drsp, void, env, fprp, fprp)
DEF_HELPER_3(drdpq, void, env, fprp, fprp)
DEF_HELPER_3(dcffix, void, env, fprp, fprp)
DEF_HELPER_3(dcffixq, void, env, fprp, fprp)
+DEF_HELPER_3(DCFFIXQQ, void, env, fprp, avr)
DEF_HELPER_3(dctfix, void, env, fprp, fprp)
DEF_HELPER_3(dctfixq, void, env, fprp, fprp)
DEF_HELPER_4(ddedpd, void, env, fprp, fprp, i32)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index 9fd8d6b817..92ea2d0739 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -43,6 +43,10 @@
&X_bfl bf l:bool ra rb
@X_bfl ...... bf:3 - l:1 ra:5 rb:5 ..........- &X_bfl
+&X_frtp_vrb frtp vrb
+%x_frtp 22:4 !function=times_2
+@X_frtp_vrb ...... ....0 ..... vrb:5 .......... . &X_frtp_vrb
frtp=%x_frtp
+
### Fixed-Point Load Instructions
LBZ 100010 ..... ..... ................ @D
@@ -121,6 +125,10 @@ SETBCR 011111 ..... ..... ----- 0110100000 -
@X_bi
SETNBC 011111 ..... ..... ----- 0111000000 - @X_bi
SETNBCR 011111 ..... ..... ----- 0111100000 - @X_bi
+### Decimal Floating-Point Conversion Instructions
+
+DCFFIXQQ 111111 ..... 00000 ..... 1111100010 - @X_frtp_vrb
+
## Vector Bit Manipulation Instruction
VCFUGED 000100 ..... ..... ..... 10101001101 @VX
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 48a484eef6..6224cb3211 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -7438,6 +7438,11 @@ static inline void set_avr64(int regno, TCGv_i64 src,
bool high)
/*
* Helpers for decodetree used by !function for decoding arguments.
*/
+static int times_2(DisasContext *ctx, int x)
+{
+ return x * 2;
+}
+
static int times_4(DisasContext *ctx, int x)
{
return x * 4;
diff --git a/target/ppc/translate/dfp-impl.c.inc
b/target/ppc/translate/dfp-impl.c.inc
index 6c556dc2e1..d5b66567a6 100644
--- a/target/ppc/translate/dfp-impl.c.inc
+++ b/target/ppc/translate/dfp-impl.c.inc
@@ -230,3 +230,20 @@ GEN_DFP_T_FPR_I32_Rc(dscriq, rA, DCM)
#undef GEN_DFP_T_A_B_I32_Rc
#undef GEN_DFP_T_B_Rc
#undef GEN_DFP_T_FPR_I32_Rc
+
+static bool trans_DCFFIXQQ(DisasContext *ctx, arg_DCFFIXQQ *a)
+{
+ TCGv_ptr rt, rb;
+
+ REQUIRE_INSNS_FLAGS2(ctx, DFP);
+ REQUIRE_FPU(ctx);
+ REQUIRE_VECTOR(ctx);
+
+ rt = gen_fprp_ptr(a->frtp);
+ rb = gen_avr_ptr(a->vrb);
+ gen_helper_DCFFIXQQ(cpu_env, rt, rb);
+ tcg_temp_free_ptr(rt);
+ tcg_temp_free_ptr(rb);
+
+ return true;
+}
--
2.25.1
