Re: [PATCH v2 11/14] target/riscv: Adjust scalar reg in vector with XLEN

[Richard Henderson]

On 11/10/21 8:04 AM, LIU Zhiwei wrote:

diff --git a/target/riscv/internals.h b/target/riscv/internals.h
index b15ad394bb..07e882160d 100644
--- a/target/riscv/internals.h
+++ b/target/riscv/internals.h
@@ -27,6 +27,7 @@ FIELD(VDATA, VM, 8, 1)
  FIELD(VDATA, LMUL, 9, 2)
  FIELD(VDATA, NF, 11, 4)
  FIELD(VDATA, WD, 11, 1)
+FIELD(VDATA, TRUNC, 15, 1)

No need for this.

@@ -4756,7 +4762,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, 
void *vs2,         \
              continue;                                                     \
          }                                                                 \
          if (i == 0) {                                                     \
-            *((ETYPE *)vd + H(i)) = s1;                                   \
+            *((ETYPE *)vd + H(i)) = trunc ? (s1 & UINT32_MAX) : s1;       \
          } else {                                                          \
              *((ETYPE *)vd + H(i)) = *((ETYPE *)vs2 + H(i - 1));           \
          }                                                                 \

...

@@ -4785,7 +4792,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, 
void *vs2,         \
              continue;                                                     \
          }                                                                 \
          if (i == vl - 1) {                                                \
-            *((ETYPE *)vd + H(i)) = s1;                                   \
+            *((ETYPE *)vd + H(i)) = trunc ? (s1 & UINT32_MAX) : s1;       \

In both of these cases you can simply zero-extend s1 in the translator before 
passing it in.


r~