The PHB v4 found on POWER9 doesn't request any LSI, so let's clear the
Interrupt Pin register in the config space so that the model matches
the hardware.
If we don't, then we inherit from the default pcie root bridge, which
requests a LSI. And because we don't map it correctly in the device
tree, all PHBs allocate the same bogus hw interrupt. We end up with
inconsistent interrupt controller (xive) data. The problem goes away
if we don't allocate the LSI in the first place.
Signed-off-by: Frederic Barrat <fbar...@linux.ibm.com>
---
hw/pci-host/pnv_phb4.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/hw/pci-host/pnv_phb4.c b/hw/pci-host/pnv_phb4.c
index 5c375a9f28..1659d55b4f 100644
--- a/hw/pci-host/pnv_phb4.c
+++ b/hw/pci-host/pnv_phb4.c
@@ -1234,10 +1234,13 @@ static void pnv_phb4_reset(DeviceState *dev)
PCIDevice *root_dev = PCI_DEVICE(&phb->root);
/*
- * Configure PCI device id at reset using a property.
+ * Configure the PCI device at reset:
+ * - set the Vendor and Device ID to for the root bridge
+ * - no LSI
*/
pci_config_set_vendor_id(root_dev->config, PCI_VENDOR_ID_IBM);
pci_config_set_device_id(root_dev->config, phb->device_id);
+ pci_config_set_interrupt_pin(root_dev->config, 0);
}
static const char *pnv_phb4_root_bus_path(PCIHostState *host_bridge,
--
2.33.1
