Hi, The skiboot merged in QEMU already has POWER10 support. This series adds a minimum set of models (XIVE2, PHB5) to boot a baremetal POWER10 machine using the OpenPOWER firmware images.
The major change is the support for the interrupt controller of the POWER10 processor. XIVE2 is very much like XIVE on POWER9 but the register interface, the different MMIO regions, the XIVE internal descriptors have gone through a major cleanup. It was easier to duplicate the models then to try to adapt the current models. XIVE2 adds some new set of features. Only some are modeled : - Address-based trigger (AB5) mode. Activated by default on the PHB5. When using ABT [1], the PHB5 offloads [2] all interrupt management on the IC, this to improve latency. - P9 compat mode. XIVE2 can be configured to provide a strict P9 interface for the TIMA. - Automatic save & restore of thread context registers. Used in KVM [3]. - 8bits thread id. Mostly to validate the model. Thanks, C. [1] https://github.com/open-power/skiboot/commit/2a7e3d203496a016cc90ce91eeb2c4e680ebd1d2 [2] https://github.com/open-power/skiboot/commit/5b2d7c79a2049c1bedfaa8a9dfa19880f980b2ef [3] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=f5af0a978776 Changes in v3: - rebased on upstream Changes in v2: - Most comments on v1 have been addressed independently and merged Cédric Le Goater (18): ppc/xive2: Introduce a XIVE2 core framework ppc/xive2: Introduce a presenter matching routine ppc/pnv: Add a XIVE2 controller to the POWER10 chip ppc/pnv: Add a OCC model for POWER10 ppc/pnv: Add POWER10 quads ppc/pnv: Add model for POWER10 PHB5 PCIe Host bridge ppc/pnv: Add a HOMER model to POWER10 ppc/psi: Add support for StoreEOI and 64k ESB pages (POWER10) ppc/xive2: Add support for notification injection on ESB pages ppc/xive: Add support for PQ state bits offload ppc/pnv: Add support for PQ offload on PHB5 ppc/pnv: Add support for PHB5 "Address-based trigger" mode pnv/xive2: Introduce new capability bits ppc/pnv: add XIVE Gen2 TIMA support pnv/xive2: Add support XIVE2 P9-compat mode (or Gen1) xive2: Add a get_config() handler for the router configuration pnv/xive2: Add support for automatic save&restore pnv/xive2: Add support for 8bits thread id hw/intc/pnv_xive2_regs.h | 442 ++++++ include/hw/pci-host/pnv_phb4.h | 11 + include/hw/pci-host/pnv_phb4_regs.h | 3 + include/hw/ppc/pnv.h | 39 + include/hw/ppc/pnv_homer.h | 3 + include/hw/ppc/pnv_occ.h | 2 + include/hw/ppc/pnv_xive.h | 71 + include/hw/ppc/pnv_xscom.h | 15 + include/hw/ppc/xive.h | 10 +- include/hw/ppc/xive2.h | 109 ++ include/hw/ppc/xive2_regs.h | 210 +++ hw/intc/pnv_xive.c | 37 +- hw/intc/pnv_xive2.c | 2127 +++++++++++++++++++++++++++ hw/intc/spapr_xive.c | 25 + hw/intc/xive.c | 77 +- hw/intc/xive2.c | 1017 +++++++++++++ hw/pci-host/pnv_phb4.c | 87 +- hw/pci-host/pnv_phb4_pec.c | 44 + hw/ppc/pnv.c | 265 +++- hw/ppc/pnv_homer.c | 64 + hw/ppc/pnv_occ.c | 16 + hw/ppc/pnv_psi.c | 38 +- hw/intc/meson.build | 4 +- hw/pci-host/trace-events | 2 + 24 files changed, 4677 insertions(+), 41 deletions(-) create mode 100644 hw/intc/pnv_xive2_regs.h create mode 100644 include/hw/ppc/xive2.h create mode 100644 include/hw/ppc/xive2_regs.h create mode 100644 hw/intc/pnv_xive2.c create mode 100644 hw/intc/xive2.c -- 2.31.1