All POWER8 machines have a maximum of 3 PHB3 devices. Adapt the PNV8_CHIP_PHB3_MAX definition for consistency.
Signed-off-by: Cédric Le Goater <c...@kaod.org> --- include/hw/ppc/pnv.h | 2 +- hw/ppc/pnv.c | 6 +++--- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h index aa08d79d24de..6f498c8f1b5f 100644 --- a/include/hw/ppc/pnv.h +++ b/include/hw/ppc/pnv.h @@ -79,7 +79,7 @@ struct Pnv8Chip { PnvOCC occ; PnvHomer homer; -#define PNV8_CHIP_PHB3_MAX 4 +#define PNV8_CHIP_PHB3_MAX 3 PnvPHB3 phbs[PNV8_CHIP_PHB3_MAX]; XICSFabric *xics; diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index 71e45515f136..bd768dcc28ad 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -1256,7 +1256,7 @@ static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data) k->chip_cfam_id = 0x221ef04980000000ull; /* P8 Murano DD2.1 */ k->cores_mask = POWER8E_CORE_MASK; - k->num_phbs = 3; + k->num_phbs = PNV8_CHIP_PHB3_MAX; k->core_pir = pnv_chip_core_pir_p8; k->intc_create = pnv_chip_power8_intc_create; k->intc_reset = pnv_chip_power8_intc_reset; @@ -1280,7 +1280,7 @@ static void pnv_chip_power8_class_init(ObjectClass *klass, void *data) k->chip_cfam_id = 0x220ea04980000000ull; /* P8 Venice DD2.0 */ k->cores_mask = POWER8_CORE_MASK; - k->num_phbs = 3; + k->num_phbs = PNV8_CHIP_PHB3_MAX; k->core_pir = pnv_chip_core_pir_p8; k->intc_create = pnv_chip_power8_intc_create; k->intc_reset = pnv_chip_power8_intc_reset; @@ -1304,7 +1304,7 @@ static void pnv_chip_power8nvl_class_init(ObjectClass *klass, void *data) k->chip_cfam_id = 0x120d304980000000ull; /* P8 Naples DD1.0 */ k->cores_mask = POWER8_CORE_MASK; - k->num_phbs = 3; + k->num_phbs = PNV8_CHIP_PHB3_MAX; k->core_pir = pnv_chip_core_pir_p8; k->intc_create = pnv_chip_power8_intc_create; k->intc_reset = pnv_chip_power8_intc_reset; -- 2.31.1