On Wed, 1 Dec 2021 at 15:40, Francisco Iglesias <francisco.igles...@xilinx.com> wrote: > > An option on real hardware when embedding a DMA engine into a peripheral > is to make the peripheral control the engine through a custom DMA control > (hardware) interface between the two. Software drivers in this scenario > configure and trigger DMA operations through the controlling peripheral's > register API (for example could writing a specific bit in a register > propagate down to a transfer start signal on the DMA control interface). > At the same time the status, results and interrupts for the transfer might > still be intended to be read and catched through the DMA engine's register > API (and signals). > > This patch adds a QEMU DMA control interface that can be used for > modelling above scenario. Through this new interface a peripheral model > embedding a DMA engine model will be able to directly initiate transfers > through the DMA. At the same time the transfer state, result and > completion signaling will be read and catched through the DMA engine > model's register API and signaling. > > Signed-off-by: Francisco Iglesias <francisco.igles...@xilinx.com>
My review of the interface is against the patch 11 documentation; please copy the typo etc fixes from there into the comments in this patch where relevant. thanks -- PMM
