We define a CPU feature for AIA CSR support in RISC-V CPUs which can be set by machine/device emulation. The RISC-V CSR emulation will also check this feature for emulating AIA CSRs.
Signed-off-by: Anup Patel <anup.pa...@wdc.com> Reviewed-by: Bin Meng <bmeng...@gmail.com> Reviewed-by: Alistair Francis <alistair.fran...@wdc.com> --- target/riscv/cpu.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 48637342ed..6e5b6acd44 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -75,7 +75,8 @@ enum { RISCV_FEATURE_MMU, RISCV_FEATURE_PMP, RISCV_FEATURE_EPMP, - RISCV_FEATURE_MISA + RISCV_FEATURE_MISA, + RISCV_FEATURE_AIA }; #define PRIV_VERSION_1_10_0 0x00011000 -- 2.25.1