On 12/21/21 10:40 PM, Cédric Le Goater wrote:
The PID SPR of the 405 CPU contains the translation ID of the TLB which is a 8-bit field. Enforce the mask with a store helper.Cc: Christophe Leroy<[email protected]> Signed-off-by: Cédric Le Goater<[email protected]> --- target/ppc/spr_tcg.h | 1 + target/ppc/cpu_init.c | 2 +- target/ppc/translate.c | 8 ++++++++ 3 files changed, 10 insertions(+), 1 deletion(-)
Reviewed-by: Richard Henderson <[email protected]> r~
