On 1/6/22 17:41, Song Gao wrote:
Signed-off-by: Song Gao<gaos...@loongson.cn>
Signed-off-by: Xiaojuan Yang<yangxiaoj...@loongson.cn>
Reviewed-by: Richard Henderson<richard.hender...@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé<f4...@amsat.org>
---
linux-user/elfload.c | 53 +++++++++++++++++++++++++++++
linux-user/loongarch64/target_elf.h | 12 +++++++
2 files changed, 65 insertions(+)
create mode 100644 linux-user/loongarch64/target_elf.h
diff --git a/linux-user/elfload.c b/linux-user/elfload.c
index 767f54c76d..2ee83778f2 100644
--- a/linux-user/elfload.c
+++ b/linux-user/elfload.c
@@ -914,6 +914,59 @@ static void elf_core_copy_regs(target_elf_gregset_t *regs,
const CPUPPCState *en
#endif
+#ifdef TARGET_LOONGARCH64
+
+#define ELF_START_MMAP 0x80000000
+
+#define ELF_CLASS ELFCLASS64
+#define ELF_ARCH EM_LOONGARCH
+
+#define elf_check_arch(x) ((x) == EM_LOONGARCH)
+static inline void init_thread(struct target_pt_regs *regs,
+ struct image_info *infop)
+{
+ regs->csr.crmd = 2 << 3;
This is just "1 << 4" and means to set the CSR.CRMD.PG bit, indicating
that page translation is enabled; it's better to explain this somehow.
(In writing this comment I realized you might be saying "0b10 << 3"
instead, because the only valid combinations for the DA and PG bits are
0b01 and 0b10; so "0b10 << 3" is also okay and maybe clearer.)
+ regs->csr.era = infop->entry;
+ regs->regs[3] = infop->start_stack;
+}
+
+/* See linux kernel: arch/loongarch/include/asm/elf.h. */
+#define ELF_NREG 45
+typedef target_elf_greg_t target_elf_gregset_t[ELF_NREG];
+
+enum {
+ TARGET_EF_R0 = 0,
+ TARGET_EF_CSR_ERA = TARGET_EF_R0 + 32,
+ TARGET_EF_CSR_BADV = TARGET_EF_R0 + 33,
+};
+
+static void elf_core_copy_regs(target_elf_gregset_t *regs,
+ const CPULoongArchState *env)
+{
+ int i;
+
+ (*regs)[TARGET_EF_R0] = 0;
+
+ for (i = 1; i < ARRAY_SIZE(env->gpr); i++) {
+ (*regs)[TARGET_EF_R0 + i] = tswapreg(env->gpr[i]);
+ }
+
+ (*regs)[TARGET_EF_CSR_ERA] = tswapreg(env->pc);
+ (*regs)[TARGET_EF_CSR_BADV] = tswapreg(env->badaddr);
+}
+
+#define USE_ELF_CORE_DUMP
+#define ELF_EXEC_PAGESIZE 4096
+
+#define ELF_HWCAP get_elf_hwcap()
+
+static uint32_t get_elf_hwcap(void)
+{
+ return 0;
+}
+
+#endif /* TARGET_LOONGARCH64 */
+
#ifdef TARGET_MIPS
#define ELF_START_MMAP 0x80000000
diff --git a/linux-user/loongarch64/target_elf.h
b/linux-user/loongarch64/target_elf.h
new file mode 100644
index 0000000000..3c690bbf5b
--- /dev/null
+++ b/linux-user/loongarch64/target_elf.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (c) 2021 Loongson Technology Corporation Limited
+ */
+
+#ifndef LOONGARCH_TARGET_ELF_H
+#define LOONGARCH_TARGET_ELF_H
+static inline const char *cpu_get_model(uint32_t eflags)
+{
+ return "Loongson-3A5000";
+}
+#endif
