On Fri, Jan 21, 2022 at 1:51 AM LIU Zhiwei <zhiwei_...@c-sky.com> wrote: > > In this patch set, we process the pc reigsters writes, > gdb reads and writes, and address calculation under > different UXLEN settings. > > The patch set v8 has been tested by running rv64 Linux with > rv32 rootfs in compat mode. You can almost follow the test [1] > given by GuoRen, except using the branch riscv-upstream-uxl-v8 > on my QEMU repo [2]. > > [1] > https://lore.kernel.org/linux-arm-kernel/20211228143958.3409187-17-guo...@kernel.org/t/ > [2] https://github.com/romanheros/qemu.git > > Except patch 22 is new, the other patches have been reviewed or acked. > > v8: > Set default XLEN for hypervisor vsstatus and mstatus_hs > > v7: > Rebase to Alistair riscv_to_apply.next branch > Add commit message for create xl field in CPURISCVState > > v6: > Pass boot 32bit rootfs on compat Linux > Pass test cases on compat OpenTee > Fix csr write mask > Fix WARL for uxl > Fix sstatus read for uxl > Relax UXL field for debugging > Don't bump machine state version for xl > Rename cpu_get_xl to cpu_recompute_xl > Rebase to vector v1.0 > Rebase to 128 bit cpu > > v5: > Add xl field in env to clear up redundant riscv_cpu_xl > Adjust pmpcfg access with mxl > Select gdb core xml according to mxl > > v4: > Support SSTATUS64_UXL write > Bump vmstate version for vill split > > v3: > Merge gen_pm_adjust_address into a canonical address function > Adjust address for RVA with XLEN > Split pm_enabled into pm_mask_enabled and pm_base_enabled > Replace array of pm tcg globals with one scalar tcg global > Split and change patch sequence > > v2: > Split out vill from vtype > Remove context switch when xlen changes at exception > Use XL instead of OL in many places > Use pointer masking and XLEN for vector address > Define an common fuction to calculate address for ld > > LIU Zhiwei (23): > target/riscv: Adjust pmpcfg access with mxl > target/riscv: Don't save pc when exception return > target/riscv: Sign extend link reg for jal and jalr > target/riscv: Sign extend pc for different XLEN > target/riscv: Create xl field in env > target/riscv: Ignore the pc bits above XLEN > target/riscv: Extend pc for runtime pc write > target/riscv: Use gdb xml according to max mxlen > target/riscv: Relax debug check for pm write > target/riscv: Adjust csr write mask with XLEN > target/riscv: Create current pm fields in env > target/riscv: Alloc tcg global for cur_pm[mask|base] > target/riscv: Calculate address according to XLEN > target/riscv: Split pm_enabled into mask and base > target/riscv: Split out the vill from vtype > target/riscv: Adjust vsetvl according to XLEN > target/riscv: Remove VILL field in VTYPE > target/riscv: Fix check range for first fault only > target/riscv: Adjust vector address with mask > target/riscv: Adjust scalar reg in vector with XLEN > target/riscv: Set default XLEN for hypervisor > target/riscv: Enable uxl field write > target/riscv: Relax UXL field for debugging
Thanks! Applied to riscv-to-apply.next Alistair > > target/riscv/cpu.c | 42 +++++++-- > target/riscv/cpu.h | 45 ++++++++- > target/riscv/cpu_bits.h | 3 + > target/riscv/cpu_helper.c | 94 +++++++++---------- > target/riscv/csr.c | 84 +++++++++++++++-- > target/riscv/gdbstub.c | 71 ++++++++++---- > target/riscv/helper.h | 4 +- > .../riscv/insn_trans/trans_privileged.c.inc | 9 +- > target/riscv/insn_trans/trans_rva.c.inc | 9 +- > target/riscv/insn_trans/trans_rvd.c.inc | 19 +--- > target/riscv/insn_trans/trans_rvf.c.inc | 19 +--- > target/riscv/insn_trans/trans_rvi.c.inc | 39 +++----- > target/riscv/insn_trans/trans_rvv.c.inc | 6 +- > target/riscv/machine.c | 16 +++- > target/riscv/op_helper.c | 7 +- > target/riscv/pmp.c | 12 +-- > target/riscv/translate.c | 90 +++++++++--------- > target/riscv/vector_helper.c | 39 +++++--- > 18 files changed, 377 insertions(+), 231 deletions(-) > > -- > 2.25.1 > >
