On Fri, 11 Feb 2022 12:07:21 +0000 Jonathan Cameron <jonathan.came...@huawei.com> wrote:
> From: Ben Widawsky <ben.widaw...@intel.com> > > A CXL memory device (AKA Type 3) is a CXL component that contains some > combination of volatile and persistent memory. It also implements the > previously defined mailbox interface as well as the memory device > firmware interface. > > Although the memory device is configured like a normal PCIe device, the > memory traffic is on an entirely separate bus conceptually (using the > same physical wires as PCIe, but different protocol). > > Once the CXL topology is fully configure and address decoders committed, > the guest physical address for the memory device is part of a larger > window which is owned by the platform. The creation of these windows > is later in this series. > > The following example will create a 256M device in a 512M window: > -object "memory-backend-file,id=cxl-mem1,share,mem-path=cxl-type3,size=512M" > -device "cxl-type3,bus=rp0,memdev=cxl-mem1,id=cxl-pmem0" > > Note: Dropped PCDIMM info interfaces for now. They can be added if > appropriate at a later date. > > Signed-off-by: Ben Widawsky <ben.widaw...@intel.com> > Signed-off-by: Jonathan Cameron <jonathan.came...@huawei.com> ... > + > +static void cxl_setup_memory(CXLType3Dev *ct3d, Error **errp) > +{ > + MemoryRegion *mr; > + > + if (!ct3d->hostmem) { > + error_setg(errp, "memdev property must be set"); > + return; > + } > + > + mr = host_memory_backend_get_memory(ct3d->hostmem); > + if (!mr) { > + error_setg(errp, "memdev property must be set"); > + return; > + } > + memory_region_set_nonvolatile(mr, true); > + memory_region_set_enabled(mr, true); > + host_memory_backend_set_mapped(ct3d->hostmem, true); > + ct3d->cxl_dstate.pmem_size = ct3d->hostmem->size; > +} > + > + > +static void ct3_realize(PCIDevice *pci_dev, Error **errp) > +{ > + CXLType3Dev *ct3d = CT3(pci_dev); > + CXLComponentState *cxl_cstate = &ct3d->cxl_cstate; > + ComponentRegisters *regs = &cxl_cstate->crb; > + MemoryRegion *mr = ®s->component_registers; > + uint8_t *pci_conf = pci_dev->config; > + > + if (!ct3d->hostmem) { Ben pointed out in reply to v5 that this is backwards. I'll fix in v7. Clearly some of the cxl_setup_memory() logic may also not be needed seeing as it wasn't running. > + cxl_setup_memory(ct3d, errp); > + } > + > + pci_config_set_prog_interface(pci_conf, 0x10); > + pci_config_set_class(pci_conf, PCI_CLASS_MEMORY_CXL); > +