Hi, In an SMP system like the sifive_u machine which has a RISCV e_cpu as hart0 and a set of u_cpus as hart 1-N, is there a way to start just the hart0 and hold the other CPUs in reset until explicitly released by hart0 SW?
I am working on a machine similar to the sifive_u machine that has a set of control registers which are accessible by hart0 to release the other cores from reset once the SoC level initialization is completed by the hart0 SW. Currently, the CPUs spin if they have a non-zero mhartid, executing code from resetvec. Vysakh P Pillai http://embeddedinn.xyz
