On Wed, 16 Feb 2022 at 07:13, Alistair Francis <alistair.fran...@opensource.wdc.com> wrote: > > From: Alistair Francis <alistair.fran...@wdc.com> > > The following changes since commit ad38520bdeb2b1e0b487db317f29119e94c1c88d: > > Merge remote-tracking branch > 'remotes/stefanha-gitlab/tags/block-pull-request' into staging (2022-02-15 > 19:30:33 +0000) > > are available in the Git repository at: > > g...@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20220216 > > for you to fetch changes up to 7035b8420fa52e8c94cf4317c0f88c1b73ced28d: > > docs/system: riscv: Update description of CPU (2022-02-16 12:25:52 +1000) > > ---------------------------------------------------------------- > Fourth RISC-V PR for QEMU 7.0 > > * Remove old Ibex PLIC header file > * Allow writing 8 bytes with generic loader > * Fixes for RV128 > * Refactor RISC-V CPU configs > * Initial support for XVentanaCondOps custom extension > * Fix for vill field in vtype > * Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode > * Support for svnapot, svinval and svpbmt extensions > > ----------------------------------------------------------------
Applied, thanks. Please update the changelog at https://wiki.qemu.org/ChangeLog/7.0 for any user-visible changes. -- PMM
