Hi, This is a few cleanups regarding user oriented life-cycle use cases. When a device is accessible to user creation, there are a few life-cycle use cases to consider: + init -> finalize (happen when introspection the object). + init -> realize-failure -> finalize (realize must report errors due to miss configuration and leave in a 'good' state)
This series fixes issues I've spotted in the riscv hart array and interrupt controllers. It is organized as follows: + patch 1 prevent memory leak in riscv array array + patch 2 introduce a new function in the riscv cpu needed by next pacthes + patches 3/4/5 prevent memory leaks and add error reporting in plic and aclint devices Thanks, -- Damien Damien Hedde (5): hw/riscv/riscv_hart: free the harts array when the object is finalized target/riscv: add riscv_cpu_release_claimed_interrupts function hw/intc/sifive_plic: report errors and free allocated memory hw/intc/riscv_aclint: swi: report errors and free allocated memory hw/intc/riscv_aclint: mtimer: report errors and free allocated memory target/riscv/cpu.h | 7 +++ hw/intc/riscv_aclint.c | 112 ++++++++++++++++++++++++++++---------- hw/intc/sifive_plic.c | 90 ++++++++++++++++++++---------- hw/riscv/riscv_hart.c | 8 +++ target/riscv/cpu_helper.c | 8 +++ 5 files changed, 168 insertions(+), 57 deletions(-) -- 2.35.1