From: Matheus Ferst <matheus.fe...@eldorado.org.br>
Implement the following PowerISA v3.1 instructions:
vcmpgtsq: Vector Compare Greater Than Signed Quadword
vcmpgtuq: Vector Compare Greater Than Unsigned Quadword
Signed-off-by: Matheus Ferst <matheus.fe...@eldorado.org.br>
---
v4:
- Branchless implementation (rth)
---
target/ppc/insn32.decode | 2 ++
target/ppc/translate/vmx-impl.c.inc | 39 +++++++++++++++++++++++++++++
2 files changed, 41 insertions(+)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index 437a3e29e0..07a4ef9103 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -388,11 +388,13 @@ VCMPGTSB 000100 ..... ..... ..... . 1100000110
@VC
VCMPGTSH 000100 ..... ..... ..... . 1101000110 @VC
VCMPGTSW 000100 ..... ..... ..... . 1110000110 @VC
VCMPGTSD 000100 ..... ..... ..... . 1111000111 @VC
+VCMPGTSQ 000100 ..... ..... ..... . 1110000111 @VC
VCMPGTUB 000100 ..... ..... ..... . 1000000110 @VC
VCMPGTUH 000100 ..... ..... ..... . 1001000110 @VC
VCMPGTUW 000100 ..... ..... ..... . 1010000110 @VC
VCMPGTUD 000100 ..... ..... ..... . 1011000111 @VC
+VCMPGTUQ 000100 ..... ..... ..... . 1010000111 @VC
VCMPNEB 000100 ..... ..... ..... . 0000000111 @VC
VCMPNEH 000100 ..... ..... ..... . 0001000111 @VC
diff --git a/target/ppc/translate/vmx-impl.c.inc
b/target/ppc/translate/vmx-impl.c.inc
index d66a642b67..4a76e370fc 100644
--- a/target/ppc/translate/vmx-impl.c.inc
+++ b/target/ppc/translate/vmx-impl.c.inc
@@ -1143,6 +1143,45 @@ static bool trans_VCMPEQUQ(DisasContext *ctx, arg_VC *a)
return true;
}
+static bool do_vcmpgtq(DisasContext *ctx, arg_VC *a, bool sign)
+{
+ TCGv_i64 t0, t1, t2;
+
+ t0 = tcg_temp_new_i64();
+ t1 = tcg_temp_new_i64();
+ t2 = tcg_temp_new_i64();
+
+ get_avr64(t0, a->vra, false);
+ get_avr64(t1, a->vrb, false);
+ tcg_gen_setcond_i64(TCG_COND_GTU, t2, t0, t1);
+
+ get_avr64(t0, a->vra, true);
+ get_avr64(t1, a->vrb, true);
+ tcg_gen_movcond_i64(TCG_COND_EQ, t2, t0, t1, t2, tcg_constant_i64(0));
+ tcg_gen_setcond_i64(sign ? TCG_COND_GT : TCG_COND_GTU, t1, t0, t1);
+
+ tcg_gen_or_i64(t1, t1, t2);
+ tcg_gen_neg_i64(t1, t1);
+
+ set_avr64(a->vrt, t1, true);
+ set_avr64(a->vrt, t1, false);
+
+ if (a->rc) {
+ tcg_gen_extrl_i64_i32(cpu_crf[6], t1);
+ tcg_gen_andi_i32(cpu_crf[6], cpu_crf[6], 0xa);
+ tcg_gen_xori_i32(cpu_crf[6], cpu_crf[6], 0x2);
+ }
+
+ tcg_temp_free_i64(t0);
+ tcg_temp_free_i64(t1);
+ tcg_temp_free_i64(t2);
+
+ return true;
+}
+
+TRANS(VCMPGTSQ, do_vcmpgtq, true)
+TRANS(VCMPGTUQ, do_vcmpgtq, false)
+
GEN_VXRFORM(vcmpeqfp, 3, 3)
GEN_VXRFORM(vcmpgefp, 3, 7)
GEN_VXRFORM(vcmpgtfp, 3, 11)
--
2.25.1
