Jonathan Cameron <jonathan.came...@huawei.com> writes:
> This adds code to instantiate the slightly extended ACPI root port
> description in DSDT as per the CXL 2.0 specification.
>
> Basically a cut and paste job from the i386/pc code.
>
> Signed-off-by: Jonathan Cameron <jonathan.came...@huawei.com>
> Signed-off-by: Ben Widawsky <ben.widaw...@intel.com>
<snip>
> @@ -139,6 +140,7 @@ void acpi_dsdt_add_gpex(Aml *scope, struct GPEXConfig
> *cfg)
> QLIST_FOREACH(bus, &bus->child, sibling) {
> uint8_t bus_num = pci_bus_num(bus);
> uint8_t numa_node = pci_bus_numa_node(bus);
> + bool is_cxl;
>
> if (!pci_bus_is_root(bus)) {
> continue;
> @@ -153,9 +155,19 @@ void acpi_dsdt_add_gpex(Aml *scope, struct GPEXConfig
> *cfg)
> nr_pcie_buses = bus_num;
> }
>
> + is_cxl = pci_bus_is_cxl(bus);
> +
nit: you could hoist the setting of is_cxl to the declaration and leave
it to the compiler to move it about if you want.
Anyway:
Reviewed-by: Alex Bennée <alex.ben...@linaro.org>
--
Alex Bennée
