On Thu, 3 Mar 2022 at 11:37, Peter Maydell <peter.mayd...@linaro.org> wrote: > > For VLD1/VST1 (single element to one lane) we are only accessing one > register, and so the 'stride' is meaningless. The bits that would > specify stride (insn bit [4] for size=1, bit [6] for size=2) are
This should say "bit [5] for size=1". > specified to be zero in the encoding (which would correspond to a > stride of 1 for VLD2/VLD3/VLD4 etc), and we must UNDEF if they are > not. -- PMM
