On Sat, Mar 5, 2022 at 10:47 PM Frank Chang <frank.ch...@sifive.com> wrote: > > Typo in patch title: > s/extenstion/extension/g >
Thanks for catching it. Will fix it. > Regards, > Frank Chang > > On Sat, Feb 26, 2022 at 3:45 PM Frank Chang <frank.ch...@sifive.com> wrote: >> >> >> >> Atish Patra <ati...@rivosinc.com> 於 2022年2月23日 週三 上午6:39寫道: >>> >>> The Linux kernel parses the ISA extensions from "riscv,isa" DT >>> property. It used to parse only the single letter base extensions >>> until now. A generic ISA extension parsing framework was proposed[1] >>> recently that can parse multi-letter ISA extensions as well. >>> >>> Generate the extended ISA string by appending the available ISA extensions >>> to the "riscv,isa" string if it is enabled so that kernel can process it. >>> >>> [1] https://lkml.org/lkml/2022/2/15/263 >>> >>> Suggested-by: Heiko Stubner <he...@sntech.de> >>> Signed-off-by: Atish Patra <ati...@rivosinc.com> >>> --- >>> Changes from v2->v3: >>> 1. Used g_strconcat to replace snprintf & a max isa string length as >>> suggested by Anup. >>> 2. I have not included the Tested-by Tag from Heiko because the >>> implementation changed from v2 to v3. >>> >>> Changes from v1->v2: >>> 1. Improved the code redability by using arrays instead of individual check >>> --- >>> target/riscv/cpu.c | 29 +++++++++++++++++++++++++++++ >>> 1 file changed, 29 insertions(+) >>> >>> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c >>> index b0a40b83e7a8..2c7ff6ef555a 100644 >>> --- a/target/riscv/cpu.c >>> +++ b/target/riscv/cpu.c >>> @@ -34,6 +34,12 @@ >>> >>> /* RISC-V CPU definitions */ >>> >>> +/* This includes the null terminated character '\0' */ >>> +struct isa_ext_data { >>> + const char *name; >>> + bool enabled; >>> +}; >>> + >>> static const char riscv_exts[26] = "IEMAFDQCLBJTPVNSUHKORWXYZG"; >>> >>> const char * const riscv_int_regnames[] = { >>> @@ -881,6 +887,28 @@ static void riscv_cpu_class_init(ObjectClass *c, void >>> *data) >>> device_class_set_props(dc, riscv_cpu_properties); >>> } >>> >>> +static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str, int >>> max_str_len) >>> +{ >>> + char *old = *isa_str; >>> + char *new = *isa_str; >>> + int i; >>> + struct isa_ext_data isa_edata_arr[] = { >>> + { "svpbmt", cpu->cfg.ext_svpbmt }, >>> + { "svinval", cpu->cfg.ext_svinval }, >>> + { "svnapot", cpu->cfg.ext_svnapot }, >> >> >> We still have other sub-extensions, e.g. Zfh, Zba, Zbb, Zbc, Zbs... etc. >> Do you mind adding them as well? >> >> Also, I think the order of ISA strings should be alphabetical as described: >> https://github.com/riscv/riscv-isa-manual/blob/master/src/naming.tex#L96 >> >> Regards, >> Frank Chang >> >>> >>> + }; >>> + >>> + for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) { >>> + if (isa_edata_arr[i].enabled) { >>> + new = g_strconcat(old, "_", isa_edata_arr[i].name, NULL); >>> + g_free(old); >>> + old = new; >>> + } >>> + } >>> + >>> + *isa_str = new; >>> +} >>> + >>> char *riscv_isa_string(RISCVCPU *cpu) >>> { >>> int i; >>> @@ -893,6 +921,7 @@ char *riscv_isa_string(RISCVCPU *cpu) >>> } >>> } >>> *p = '\0'; >>> + riscv_isa_string_ext(cpu, &isa_str, maxlen); >>> return isa_str; >>> } >>> >>> -- >>> 2.30.2 >>> -- Regards, Atish