From: Bin Meng <bin.m...@windriver.com> Add a config option to enable support for native M-mode debug. This is disabled by default and can be enabled with 'debug=true'.
Signed-off-by: Bin Meng <bin.m...@windriver.com> Reviewed-by: Alistair Francis <alistair.fran...@wdc.com> --- (no changes since v2) Changes in v2: - change the config option to 'disabled' by default target/riscv/cpu.h | 4 +++- target/riscv/cpu.c | 5 +++++ 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index ad35129239..d3e884452b 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -79,7 +79,8 @@ enum { RISCV_FEATURE_PMP, RISCV_FEATURE_EPMP, RISCV_FEATURE_MISA, - RISCV_FEATURE_AIA + RISCV_FEATURE_AIA, + RISCV_FEATURE_DEBUG }; #define PRIV_VERSION_1_10_0 0x00011000 @@ -388,6 +389,7 @@ struct RISCVCPUConfig { bool pmp; bool epmp; bool aia; + bool debug; uint64_t resetvec; }; diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 6a4c94da2a..eb2be5fa05 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -541,6 +541,10 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) riscv_set_feature(env, RISCV_FEATURE_AIA); } + if (cpu->cfg.debug) { + riscv_set_feature(env, RISCV_FEATURE_DEBUG); + } + set_resetvec(env, cpu->cfg.resetvec); /* Validate that MISA_MXL is set properly. */ @@ -780,6 +784,7 @@ static Property riscv_cpu_properties[] = { DEFINE_PROP_BOOL("Zve64f", RISCVCPU, cfg.ext_zve64f, false), DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true), DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true), + DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, false), DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec), DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec), -- 2.25.1