On 3/27/22 03:34, Idan Horowitz wrote:
As per the AArch64.SS2InitialTTWState() psuedo-code in the ARMv8 ARM the
initial PA space used for stage 2 table walks is assigned based on the SW
and NSW bits of the VSTCR and VTCR registers.
This was already implemented for the recursive stage 2 page table walks
in S1_ptw_translate(), but was missing for the final stage 2 walk.
Signed-off-by: Idan Horowitz<idan.horow...@gmail.com>
---
target/arm/helper.c | 10 ++++++++++
1 file changed, 10 insertions(+)
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
r~
