On Fri, 1 Apr 2022 at 00:50, Alistair Francis <alistair.fran...@opensource.wdc.com> wrote: > > From: Alistair Francis <alistair.fran...@wdc.com> > > The following changes since commit d5341e09135b871199073572f53bc11ae9b44897: > > Merge tag 'pull-tcg-20220331' of https://gitlab.com/rth7680/qemu into > staging (2022-03-31 18:36:08 +0100) > > are available in the Git repository at: > > g...@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20220401 > > for you to fetch changes up to 8ff8ac63298611c8373b294ec936475b1a33f63f: > > target/riscv: rvv: Add missing early exit condition for whole register > load/store (2022-04-01 08:40:55 +1000) > > ---------------------------------------------------------------- > Sixth RISC-V PR for QEMU 7.0 > > This is a last minute RISC-V PR for 7.0. > > It includes a fix to avoid leaking no translation TLB entries. This > incorrectly cached uncachable baremetal entries. This would break Linux > boot while single stepping. As the fix is pretty straight forward (flush > the cache more often) it's being pulled in for 7.0. > > At the same time I have included a RISC-V vector extension fixup patch. > > ----------------------------------------------------------------
Applied, thanks. Please update the changelog at https://wiki.qemu.org/ChangeLog/7.0 for any user-visible changes. -- PMM
