From: "Lucas Mateus Castro (alqotel)" <lucas.ara...@eldorado.org.br>
This patch series is an implementation of the vector divide, vector divide extended and vector modulo instructions from PowerISA 3.1 The first patch are Matheus' patch, used here since the divs256 and divu256 functions use int128_urshift. v2 changes: - Dropped int128_lshift patch - Added missing int_min/-1 check - Changed invalid division to a division by 1 - Created new macro responsible for invalid division check (replacing DIV_VEC, REM_VEC and the check in dives_i32/diveu_i32) - Turned GVecGen3 array into single element Lucas Mateus Castro (alqotel) (8): target/ppc: Implemented vector divide instructions target/ppc: Implemented vector divide quadword target/ppc: Implemented vector divide extended word host-utils: Implemented unsigned 256-by-128 division host-utils: Implemented signed 256-by-128 division target/ppc: Implemented remaining vector divide extended target/ppc: Implemented vector module word/doubleword target/ppc: Implemented vector module quadword Matheus Ferst (1): qemu/int128: add int128_urshift include/qemu/host-utils.h | 16 +++ include/qemu/int128.h | 39 ++++++ target/ppc/helper.h | 8 ++ target/ppc/insn32.decode | 23 ++++ target/ppc/int_helper.c | 106 ++++++++++++++++ target/ppc/translate/vmx-impl.c.inc | 125 +++++++++++++++++++ tests/unit/test-int128.c | 32 +++++ util/host-utils.c | 179 ++++++++++++++++++++++++++++ 8 files changed, 528 insertions(+) -- 2.31.1