> -----Original Message-----
> From: Edgar E. Iglesias <edgar.igles...@xilinx.com>
> Sent: 06 April 2022 18:43
> To: qemu-devel@nongnu.org
> Cc: qemu-...@nongnu.org; peter.mayd...@linaro.org;
> richard.hender...@linaro.org; alist...@alistair23.me; l...@lmichel.fr;
> f4...@amsat.org; frasse.igles...@gmail.com; Francisco Eduardo Iglesias
> <figle...@xilinx.com>; Sai Pavan Boddu <saip...@xilinx.com>; Frederic
> Konrad <fkon...@xilinx.com>; Edgar Iglesias <edg...@xilinx.com>;
> edgar.igles...@amd.com
> Subject: [PATCH v1 4/4] hw/arm: versal: Connect the CRL
>
> From: "Edgar E. Iglesias" <edgar.igles...@amd.com>
>
> Connect the CRL (Clock Reset LPD) to the Versal SoC.
>
> Signed-off-by: Edgar E. Iglesias <edgar.igles...@amd.com>
> ---
> hw/arm/xlnx-versal.c | 54 ++++++++++++++++++++++++++++++++++--
> include/hw/arm/xlnx-versal.h | 4 +++
> 2 files changed, 56 insertions(+), 2 deletions(-)
>
> diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c
> index ebad8dbb6d..57276e1506 100644
> --- a/hw/arm/xlnx-versal.c
> +++ b/hw/arm/xlnx-versal.c
> @@ -539,6 +539,57 @@ static void versal_create_ospi(Versal *s, qemu_irq
> *pic)
> qdev_connect_gpio_out(orgate, 0, pic[VERSAL_OSPI_IRQ]);
> }
>
> +static void versal_create_crl(Versal *s, qemu_irq *pic)
> +{
> + SysBusDevice *sbd;
> + int i;
> +
> + object_initialize_child(OBJECT(s), "crl", &s->lpd.crl,
> + TYPE_XLNX_VERSAL_CRL);
> + sbd = SYS_BUS_DEVICE(&s->lpd.crl);
> +
> + for (i = 0; i < ARRAY_SIZE(s->lpd.rpu.cpu); i++) {
> + g_autofree gchar *name = g_strdup_printf("cpu_r5[%d]", i);
> +
> + object_property_set_link(OBJECT(&s->lpd.crl),
> + name, OBJECT(&s->lpd.rpu.cpu[i]),
> + &error_abort);
> + }
> +
> + for (i = 0; i < ARRAY_SIZE(s->lpd.iou.gem); i++) {
> + g_autofree gchar *name = g_strdup_printf("gem[%d]", i);
> +
> + object_property_set_link(OBJECT(&s->lpd.crl),
> + name, OBJECT(&s->lpd.iou.gem[i]),
> + &error_abort);
> + }
> +
> + for (i = 0; i < ARRAY_SIZE(s->lpd.iou.adma); i++) {
> + g_autofree gchar *name = g_strdup_printf("adma[%d]", i);
> +
> + object_property_set_link(OBJECT(&s->lpd.crl),
> + name, OBJECT(&s->lpd.iou.adma[i]),
> + &error_abort);
> + }
> +
> + for (i = 0; i < ARRAY_SIZE(s->lpd.iou.uart); i++) {
> + g_autofree gchar *name = g_strdup_printf("uart[%d]", i);
> +
> + object_property_set_link(OBJECT(&s->lpd.crl),
> + name, OBJECT(&s->lpd.iou.uart[i]),
> + &error_abort);
> + }
> +
> + object_property_set_link(OBJECT(&s->lpd.crl),
> + "usb", OBJECT(&s->lpd.iou.usb),
> + &error_abort);
> +
> + sysbus_realize(sbd, &error_fatal);
> + memory_region_add_subregion(&s->mr_ps, MM_CRL,
> + sysbus_mmio_get_region(sbd, 0));
> + sysbus_connect_irq(sbd, 0, pic[VERSAL_CRL_IRQ]);
> +}
> +
> /* This takes the board allocated linear DDR memory and creates aliases
> * for each split DDR range/aperture on the Versal address map.
> */
> @@ -622,8 +673,6 @@ static void versal_unimp(Versal *s)
>
> versal_unimp_area(s, "psm", &s->mr_ps,
> MM_PSM_START, MM_PSM_END - MM_PSM_START);
> - versal_unimp_area(s, "crl", &s->mr_ps,
> - MM_CRL, MM_CRL_SIZE);
> versal_unimp_area(s, "crf", &s->mr_ps,
> MM_FPD_CRF, MM_FPD_CRF_SIZE);
> versal_unimp_area(s, "apu", &s->mr_ps,
> @@ -681,6 +730,7 @@ static void versal_realize(DeviceState *dev, Error
> **errp)
> versal_create_efuse(s, pic);
> versal_create_pmc_iou_slcr(s, pic);
> versal_create_ospi(s, pic);
> + versal_create_crl(s, pic);
> versal_map_ddr(s);
> versal_unimp(s);
>
> diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h
> index 155e8c4b8c..cbe8a19c10 100644
> --- a/include/hw/arm/xlnx-versal.h
> +++ b/include/hw/arm/xlnx-versal.h
> @@ -29,6 +29,7 @@
> #include "hw/nvram/xlnx-versal-efuse.h"
> #include "hw/ssi/xlnx-versal-ospi.h"
> #include "hw/dma/xlnx_csu_dma.h"
> +#include "hw/misc/xlnx-versal-crl.h"
> #include "hw/misc/xlnx-versal-pmc-iou-slcr.h"
>
> #define TYPE_XLNX_VERSAL "xlnx-versal"
> @@ -87,6 +88,8 @@ struct Versal {
> qemu_or_irq irq_orgate;
> XlnxXramCtrl ctrl[XLNX_VERSAL_NR_XRAM];
> } xram;
> +
> + XlnxVersalCRL crl;
> } lpd;
>
> /* The Platform Management Controller subsystem. */
> @@ -127,6 +130,7 @@ struct Versal {
> #define VERSAL_TIMER_NS_EL1_IRQ 14
> #define VERSAL_TIMER_NS_EL2_IRQ 10
>
> +#define VERSAL_CRL_IRQ 10
> #define VERSAL_UART0_IRQ_0 18
> #define VERSAL_UART1_IRQ_0 19
> #define VERSAL_USB0_IRQ_0 22
> --
> 2.25.1
Reviewed-by: Frederic Konrad <fkon...@amd.com>
