This extension concerns branch speculation, which TCG does not implement. Thus we can trivially enable this feature.
Signed-off-by: Richard Henderson <richard.hender...@linaro.org> --- target/arm/cpu64.c | 1 + target/arm/cpu_tcg.c | 1 + 2 files changed, 2 insertions(+) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index def0f1fdcb..c1006a067c 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -805,6 +805,7 @@ static void aarch64_max_initfn(Object *obj) t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1); t = FIELD_DP64(t, ID_AA64PFR0, SEL2, 1); /* FEAT_SEL2 */ t = FIELD_DP64(t, ID_AA64PFR0, DIT, 1); /* FEAT_DIT */ + t = FIELD_DP64(t, ID_AA64PFR0, CSV2, 1); /* FEAT_CSV2 */ cpu->isar.id_aa64pfr0 = t; t = cpu->isar.id_aa64pfr1; diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c index 5cce9116d0..2750cbebec 100644 --- a/target/arm/cpu_tcg.c +++ b/target/arm/cpu_tcg.c @@ -71,6 +71,7 @@ void arm32_max_features(ARMCPU *cpu) cpu->isar.id_mmfr4 = t; t = cpu->isar.id_pfr0; + t = FIELD_DP32(t, ID_PFR0, CSV2, 2); /* FEAT_CVS2 */ t = FIELD_DP32(t, ID_PFR0, DIT, 1); /* FEAT_DIT */ t = FIELD_DP32(t, ID_PFR0, RAS, 1); /* FEAT_RAS */ cpu->isar.id_pfr0 = t; -- 2.25.1