On Sat, 9 Apr 2022 at 01:23, Richard Henderson <richard.hender...@linaro.org> wrote: > > This feature is AArch64 only, and applies to physical SErrors, > which QEMU does not implement, thus the feature is a nop. > > Signed-off-by: Richard Henderson <richard.hender...@linaro.org> > --- > target/arm/cpu64.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c > index 03c6707111..def0f1fdcb 100644 > --- a/target/arm/cpu64.c > +++ b/target/arm/cpu64.c > @@ -838,6 +838,7 @@ static void aarch64_max_initfn(Object *obj) > t = cpu->isar.id_aa64mmfr2; > t = FIELD_DP64(t, ID_AA64MMFR2, CNP, 1); /* FEAT_TTCNP */ > t = FIELD_DP64(t, ID_AA64MMFR2, UAO, 1); /* FEAT_UAO */ > + t = FIELD_DP64(t, ID_AA64MMFR2, IESB, 1); /* FEAT_IESB */ > t = FIELD_DP64(t, ID_AA64MMFR2, VARANGE, 1); /* FEAT_LVA */ > t = FIELD_DP64(t, ID_AA64MMFR2, ST, 1); /* FEAT_TTST */ > cpu->isar.id_aa64mmfr2 = t; > -- > 2.25.1
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org> thanks -- PMM