Use the qemu_fdt_setprop_reg64() to replace the code that sets the property manually.
Signed-off-by: Ben Dooks <q...@ben.fluff.org> --- hw/riscv/sifive_u.c | 41 +++++++++++------------------------------ 1 file changed, 11 insertions(+), 30 deletions(-) diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 7fbc7dea42..1fe364cbb0 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -223,9 +223,7 @@ static void create_fdt(SiFiveUState *s, const MemMapEntry *memmap, qemu_fdt_add_subnode(fdt, nodename); qemu_fdt_setprop_string_array(fdt, nodename, "compatible", (char **)&clint_compat, ARRAY_SIZE(clint_compat)); - qemu_fdt_setprop_cells(fdt, nodename, "reg", - 0x0, memmap[SIFIVE_U_DEV_CLINT].base, - 0x0, memmap[SIFIVE_U_DEV_CLINT].size); + qemu_fdt_setprop_reg64(fdt, nodename, &memmap[SIFIVE_U_DEV_CLINT]); qemu_fdt_setprop(fdt, nodename, "interrupts-extended", cells, ms->smp.cpus * sizeof(uint32_t) * 4); g_free(cells); @@ -235,9 +233,7 @@ static void create_fdt(SiFiveUState *s, const MemMapEntry *memmap, (long)memmap[SIFIVE_U_DEV_OTP].base); qemu_fdt_add_subnode(fdt, nodename); qemu_fdt_setprop_cell(fdt, nodename, "fuse-count", SIFIVE_U_OTP_REG_SIZE); - qemu_fdt_setprop_cells(fdt, nodename, "reg", - 0x0, memmap[SIFIVE_U_DEV_OTP].base, - 0x0, memmap[SIFIVE_U_DEV_OTP].size); + qemu_fdt_setprop_reg64(fdt, nodename, &memmap[SIFIVE_U_DEV_OTP]); qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,fu540-c000-otp"); g_free(nodename); @@ -250,9 +246,7 @@ static void create_fdt(SiFiveUState *s, const MemMapEntry *memmap, qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x1); qemu_fdt_setprop_cells(fdt, nodename, "clocks", hfclk_phandle, rtcclk_phandle); - qemu_fdt_setprop_cells(fdt, nodename, "reg", - 0x0, memmap[SIFIVE_U_DEV_PRCI].base, - 0x0, memmap[SIFIVE_U_DEV_PRCI].size); + qemu_fdt_setprop_reg64(fdt, nodename, &memmap[SIFIVE_U_DEV_PRCI]); qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,fu540-c000-prci"); g_free(nodename); @@ -284,9 +278,7 @@ static void create_fdt(SiFiveUState *s, const MemMapEntry *memmap, qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0); qemu_fdt_setprop(fdt, nodename, "interrupts-extended", cells, (ms->smp.cpus * 4 - 2) * sizeof(uint32_t)); - qemu_fdt_setprop_cells(fdt, nodename, "reg", - 0x0, memmap[SIFIVE_U_DEV_PLIC].base, - 0x0, memmap[SIFIVE_U_DEV_PLIC].size); + qemu_fdt_setprop_reg64(fdt, nodename, &memmap[SIFIVE_U_DEV_PLIC]); qemu_fdt_setprop_cell(fdt, nodename, "riscv,ndev", 0x35); qemu_fdt_setprop_cell(fdt, nodename, "phandle", plic_phandle); plic_phandle = qemu_fdt_get_phandle(fdt, nodename); @@ -304,9 +296,7 @@ static void create_fdt(SiFiveUState *s, const MemMapEntry *memmap, qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0); qemu_fdt_setprop_cell(fdt, nodename, "#gpio-cells", 2); qemu_fdt_setprop(fdt, nodename, "gpio-controller", NULL, 0); - qemu_fdt_setprop_cells(fdt, nodename, "reg", - 0x0, memmap[SIFIVE_U_DEV_GPIO].base, - 0x0, memmap[SIFIVE_U_DEV_GPIO].size); + qemu_fdt_setprop_reg64(fdt, nodename, &memmap[SIFIVE_U_DEV_GPIO]); qemu_fdt_setprop_cells(fdt, nodename, "interrupts", SIFIVE_U_GPIO_IRQ0, SIFIVE_U_GPIO_IRQ1, SIFIVE_U_GPIO_IRQ2, SIFIVE_U_GPIO_IRQ3, SIFIVE_U_GPIO_IRQ4, SIFIVE_U_GPIO_IRQ5, SIFIVE_U_GPIO_IRQ6, @@ -342,9 +332,7 @@ static void create_fdt(SiFiveUState *s, const MemMapEntry *memmap, nodename = g_strdup_printf("/soc/cache-controller@%lx", (long)memmap[SIFIVE_U_DEV_L2CC].base); qemu_fdt_add_subnode(fdt, nodename); - qemu_fdt_setprop_cells(fdt, nodename, "reg", - 0x0, memmap[SIFIVE_U_DEV_L2CC].base, - 0x0, memmap[SIFIVE_U_DEV_L2CC].size); + qemu_fdt_setprop_reg64(fdt, nodename, &memmap[SIFIVE_U_DEV_L2CC]); qemu_fdt_setprop_cells(fdt, nodename, "interrupts", SIFIVE_U_L2CC_IRQ0, SIFIVE_U_L2CC_IRQ1, SIFIVE_U_L2CC_IRQ2); qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); @@ -366,9 +354,7 @@ static void create_fdt(SiFiveUState *s, const MemMapEntry *memmap, prci_phandle, PRCI_CLK_TLCLK); qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_QSPI2_IRQ); qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); - qemu_fdt_setprop_cells(fdt, nodename, "reg", - 0x0, memmap[SIFIVE_U_DEV_QSPI2].base, - 0x0, memmap[SIFIVE_U_DEV_QSPI2].size); + qemu_fdt_setprop_reg64(fdt, nodename, &memmap[SIFIVE_U_DEV_QSPI2]); qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,spi0"); g_free(nodename); @@ -391,9 +377,7 @@ static void create_fdt(SiFiveUState *s, const MemMapEntry *memmap, prci_phandle, PRCI_CLK_TLCLK); qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_QSPI0_IRQ); qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); - qemu_fdt_setprop_cells(fdt, nodename, "reg", - 0x0, memmap[SIFIVE_U_DEV_QSPI0].base, - 0x0, memmap[SIFIVE_U_DEV_QSPI0].size); + qemu_fdt_setprop_reg64(fdt, nodename, &memmap[SIFIVE_U_DEV_QSPI0]); qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,spi0"); g_free(nodename); @@ -449,9 +433,8 @@ static void create_fdt(SiFiveUState *s, const MemMapEntry *memmap, (long)memmap[SIFIVE_U_DEV_PWM0].base); qemu_fdt_add_subnode(fdt, nodename); qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,pwm0"); - qemu_fdt_setprop_cells(fdt, nodename, "reg", - 0x0, memmap[SIFIVE_U_DEV_PWM0].base, - 0x0, memmap[SIFIVE_U_DEV_PWM0].size); +qemu_fdt_setprop_reg64(fdt, nodename, &memmap[SIFIVE_U_DEV_PWM0]); + qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); qemu_fdt_setprop_cells(fdt, nodename, "interrupts", SIFIVE_U_PWM0_IRQ0, SIFIVE_U_PWM0_IRQ1, @@ -496,9 +479,7 @@ static void create_fdt(SiFiveUState *s, const MemMapEntry *memmap, (long)memmap[SIFIVE_U_DEV_UART0].base); qemu_fdt_add_subnode(fdt, nodename); qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,uart0"); - qemu_fdt_setprop_cells(fdt, nodename, "reg", - 0x0, memmap[SIFIVE_U_DEV_UART0].base, - 0x0, memmap[SIFIVE_U_DEV_UART0].size); + qemu_fdt_setprop_reg64(fdt, nodename, &memmap[SIFIVE_U_DEV_UART0]); qemu_fdt_setprop_cells(fdt, nodename, "clocks", prci_phandle, PRCI_CLK_TLCLK); qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); -- 2.35.1