Excerpts from Cédric Le Goater's message of April 21, 2022 4:21 pm: > On 4/21/22 04:04, Nicholas Piggin wrote: >> Excerpts from Leandro Lupori's message of April 21, 2022 4:09 am: >>> On 4/18/22 17:22, Cédric Le Goater wrote: >>>> On 4/18/22 21:10, Leandro Lupori wrote: >>>>> Add semihosting support for PPC64. This implementation is >>>>> based on the standard for ARM semihosting version 2.0, as >>>>> implemented by QEMU and documented in >>>>> >>>>> https://github.com/ARM-software/abi-aa/releases >>>>> >>>>> The PPC64 specific differences are the following: >>>>> >>>>> Semihosting Trap Instruction: sc 7 >>>>> Operation Number Register: r3 >>>>> Parameter Register: r4 >>>>> Return Register: r3 >>>>> Data block field size: 64 bits >>>> >>>> 'sc' is a good way to implement semi hosting but we should make sure >>>> that it is not colliding with future extensions, at least with the >>>> next POWERPC processor. Is that the case ? if not, then the lev could >>>> be reserved. >>>> >>> >>> Power ISA 3.1B says that LEV values greater that 2 are reserved. >>> Level 2 is the ultravisor, so I assumed that level 7 was far enough from >>> current max level. I don't know if POWER11 will introduce new privilege >>> levels. Is this info publicly available somewhere? Or do you have a >>> better level in mind to use instead? >> >> It's not available but there are no plans to use LEV=7. >> >> It would be fine in practice I think, but it's kind of ugly and not >> great precedent -- how would we find out all the projects which use >> reserved instructions or values for something? Nominally the onus is on >> the software to accept breakage, but in reality important software that >> breaks causes a headache for the ISA. >> >> IBM's systemsim emulator actually has an instruction to call out to the >> emulator to do various things like IO. It uses the opcode >> >> .long 0x000eaeb0 >> >> That is the primary op 0 reserved space, and there is actually another >> op 'attn' or 'sp_attn' there which IBM CPUs implement, it is similar in >> spirit (it calls out to the service processor and/or chip error handling >> system to deal with a condition out-of-band). You don't want to use attn >> here because the core under emulation might implement it, I'm just >> noting the precedent with similar functionality under this primary >> opcode. >> >> So I think the systemsim emulator instruction should be a good choice. > > yeah. It's not a major change. > >> But it should really be documented. I will bring this up at the Open >> Power ISA working group meeting next week and see what the options are >> with getting it formally allocated for semihosting emulators (or what >> the alternatives are). > > It would be nice to invite Leandro to this meeting since he started > implementing.
Good point. I'll organize with him offline. Thanks, Nick