According to v-spec, tail agnostic behavior can be either kept as
undisturbed or set elements' bits to all 1s. To distinguish the
difference of tail policies, QEMU should be able to simulate the tail
agnostic behavior as "set tail elements' bits to all 1s". An option
'rvv_ta_all_1s' is added to enable the behavior, it is default as
disabled.
There are multiple possibility for agnostic elements according to
v-spec. The main intent of this patch-set tries to add option that
can distinguish between tail policies. Setting agnostic elements to
all 1s makes things simple and allow QEMU to express this.
We may explore other possibility of agnostic behavior by adding
other options in the future. Please understand that this patch-set
is limited.
v2 updates:
- Addressed comments from Weiwei Li
- Added commit tail agnostic on load / store instructions (which
I forgot to include into the patch-set)
v3 updates:
- Missed the very 1st commit, adding it back
v4 updates:
- Renamed vlmax to total_elems
- Deal with tail element when vl_eq_vlmax == true
v5 updates:
- Let `vext_get_total_elems` take `desc` and `esz`
- Utilize `simd_maxsz(desc)` to get `vlenb`
- Fix alignments to code
v6 updates:
- Fix `vext_get_total_elems`
v7 updates:
- Reuse `max_elems` for vector load / store helper functions. The
translation sets desc's `lmul` to `min(1, lmul)`, making
`vext_max_elems` equivalent to `vext_get_total_elems`.
v8 updates:
- Simplify `vext_set_elems_1s`, don't need `vext_set_elems_1s_fns`
- Fix `vext_get_total_elems`, it should derive upon EMUL instead
of LMUL
v9 updates:
- Let instructions that is tail agnostic regardless of vta respect the
option and not the vta.
eopXD (14):
target/riscv: rvv: Prune redundant ESZ, DSZ parameter passed
target/riscv: rvv: Rename ambiguous esz
target/riscv: rvv: Early exit when vstart >= vl
target/riscv: rvv: Add tail agnostic for vv instructions
target/riscv: rvv: Add tail agnostic for vector load / store
instructions
target/riscv: rvv: Add tail agnostic for vx, vvm, vxm instructions
target/riscv: rvv: Add tail agnostic for vector integer shift
instructions
target/riscv: rvv: Add tail agnostic for vector integer comparison
instructions
target/riscv: rvv: Add tail agnostic for vector integer merge and move
instructions
target/riscv: rvv: Add tail agnostic for vector fix-point arithmetic
instructions
target/riscv: rvv: Add tail agnostic for vector floating-point
instructions
target/riscv: rvv: Add tail agnostic for vector reduction instructions
target/riscv: rvv: Add tail agnostic for vector mask instructions
target/riscv: rvv: Add tail agnostic for vector permutation
instructions
target/riscv/cpu.c | 1 +
target/riscv/cpu.h | 2 +
target/riscv/cpu_helper.c | 2 +
target/riscv/insn_trans/trans_rvv.c.inc | 176 +++
target/riscv/internals.h | 6 +-
target/riscv/translate.c | 4 +
target/riscv/vector_helper.c | 1536 ++++++++++++++---------
7 files changed, 1110 insertions(+), 617 deletions(-)
--
2.34.2
