In the original Arm v8 two-stage translation, both stage 1 and stage 2 specify memory attributes (memory type, cacheability, shareability); these are then combined to produce the overall memory attributes for the whole stage 1+2 access.
The new FEAT_S2FWB feature allows the guest to enable a different interpretation of the attribute bits in the stage 2 descriptors. These bits can now be used to control details of how the stage 1 and 2 attributes should be combined (for instance they can say "always use the stage 1 attributes" or "ignore the stage 1 attributes and always be Device memory"). This series implements support for FEAT_S2FWB. It starts by postponing interpretation of the attribute bits in a stage 2 descriptor until the point where we need to combine them with the stage 1 attributes. It then pulls out the HCR_EL2.FWB=0 specific code into its own function, so that the support for FWB=1 that we add in patch 3 slots in neatly. Finally, patch 4 turns it on for -cpu max. I have tested that a Linux nested-guest setup works OK (and that the guest really is turning on HCR_EL2.FWB), but since we don't do anything with memory attributes except return them in the PAR_EL1 when the guest does AT instructions, you probably wouldn't find bugs in this unless you explicitly went and wrote a bunch of test cases that set up page tables and ran AT instructions to check what memory attributes we report. -- PMM Peter Maydell (4): target/arm: Postpone interpretation of stage 2 descriptor attribute bits target/arm: Factor out FWB=0 specific part of combine_cacheattrs() target/arm: Implement FEAT_S2FWB target/arm: Enable FEAT_S2FWB for -cpu max docs/system/arm/emulation.rst | 1 + target/arm/cpu.h | 5 + target/arm/internals.h | 7 +- target/arm/cpu64.c | 10 ++ target/arm/helper.c | 200 +++++++++++++++++++++++++++------- 5 files changed, 182 insertions(+), 41 deletions(-) -- 2.25.1
