Hi, Peter. > Shuuichirou, Itaru: do either of you know the right setting for the A64FX for > this? If > you can find what the hardware value of the ICC_CTLR_EL3 or ICC_CTLR_EL1 > register is (more specifically, the PRIBits subfield) that should be enough > to tell > us.
The value of the PRIbits field in the A64FX is 0x4. Therefore, the following values is fine. > > + cpu->gic_pribits = 5; Best regards, Shuuichirou. P.S. Itaru, thank you for the follow-up. > -----Original Message----- > From: Peter Maydell <peter.mayd...@linaro.org> > Sent: Saturday, May 7, 2022 1:34 AM > To: qemu-...@nongnu.org; qemu-devel@nongnu.org > Cc: Ishii, Shuuichirou/石井 周一郎 <ishii.shuuic...@fujitsu.com>; Itaru Kitayama > <itaru.kitay...@gmail.com> > Subject: Re: [PATCH 4/5] hw/intc/arm_gicv3: Use correct number of priority > bits > for the CPU > > On Fri, 6 May 2022 at 17:21, Peter Maydell <peter.mayd...@linaro.org> wrote: > > > > Make the GICv3 set its number of bits of physical priority from the > > implementation-specific value provided in the CPU state struct, in the > > same way we already do for virtual priority bits. Because this would > > be a migration compatibility break, we provide a property > > force-8-bit-prio which is enabled for 7.0 and earlier versioned board > > models to retain the legacy "always use 8 bits" behaviour. > > > > Signed-off-by: Peter Maydell <peter.mayd...@linaro.org> > > --- > > I have guessed at the right value for the A64FX, but if we can find > > the correct ICC_CTLR_EL1 value that would be better. > > Shuuichirou, Itaru: do either of you know the right setting for the A64FX for > this? If > you can find what the hardware value of the ICC_CTLR_EL3 or ICC_CTLR_EL1 > register is (more specifically, the PRIBits subfield) that should be enough > to tell > us. > > > @@ -961,6 +964,12 @@ static void aarch64_a64fx_initfn(Object *obj) > > cpu->gic_num_lrs = 4; > > cpu->gic_vpribits = 5; > > cpu->gic_vprebits = 5; > > + /* > > + * TODO: What does the real A64FX GICv3 provide ? > > + * This is a guess based on what other Arm CPUs do; to find the correct > > + * answer we need the value of the A64FX's ICC_CTLR_EL1 register. > > + */ > > + cpu->gic_pribits = 5; > > > > /* Suppport of A64FX's vector length are 128,256 and 512bit only */ > > aarch64_add_sve_properties(obj); > > -- > > 2.25.1 > > thanks > -- PMM
