Re: [PATCH v3 34/43] hw/intc: Add LoongArch extioi interrupt controller(EIOINTC)

[yangxiaojuan]

On 2022/5/10 上午1:56, Richard Henderson wrote:
On 5/9/22 04:38, yangxiaojuan wrote:
You are not considering CSR[0x420][49], which changes the format of 
this mapping.

Thanks very much, I will consider the mapping format by read 
iocsr[0x420][49] like this:
static uint64_t map_format(void)
{
     LoongArchCPU *cpu;
     CPULoongArchState *env;
     uint64_t val;

     cpu = LOONGARCH_CPU(current_cpu);
     env = &(cpu->env);

     val = address_space_ldq(&env->address_space_iocsr, 0x420,
                              MEMTXATTRS_UNSPECIFIED, NULL);
     val &= 1 << 49;
     return val;
}

I'm not 100% sure how this "Other configuration control register" 
should be handled, but definitely not like this. 
Could we use the bitmapping as the default cpu or ip map format? Becaue 
we emulate iocsr[0x420] as a default value, and it does not support to 
write. We will add 'TOOD' logs and continue to modify them when using 
other routing methods later.
What do you think of this idea？

Thanks.
Xiaojuan