On Tue, May 17, 2022 at 12:21 PM Weiwei Li <liwei...@iscas.ac.cn> wrote: > > - properties for zb* extensions are enabled by default which will make > sifive/ibex cpu types implicitly support zb* extensions > > Signed-off-by: Weiwei Li <liwei...@iscas.ac.cn> > Signed-off-by: Junqiang Wang <wangjunqi...@iscas.ac.cn> > --- > target/riscv/cpu.c | 24 ++++++++++++++++++++++++ > 1 file changed, 24 insertions(+) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index b12f69c584..e205be34e9 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -176,6 +176,10 @@ static void rv64_sifive_u_cpu_init(Object *obj) > CPURISCVState *env = &RISCV_CPU(obj)->env; > set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); > set_priv_version(env, PRIV_VERSION_1_10_0); > + qdev_prop_set_bit(DEVICE(obj), "zba", false); > + qdev_prop_set_bit(DEVICE(obj), "zbb", false); > + qdev_prop_set_bit(DEVICE(obj), "zbc", false); > + qdev_prop_set_bit(DEVICE(obj), "zbs", false);
This is very error prone. I think we should either disable the extensions by default, then enable them for the rv32/rv64 CPUs, or instead do something like this: https://patchew.org/QEMU/20220517041100.93045-1-alistair.fran...@opensource.wdc.com/ Alistair > } > > static void rv64_sifive_e_cpu_init(Object *obj) > @@ -184,6 +188,10 @@ static void rv64_sifive_e_cpu_init(Object *obj) > set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU); > set_priv_version(env, PRIV_VERSION_1_10_0); > qdev_prop_set_bit(DEVICE(obj), "mmu", false); > + qdev_prop_set_bit(DEVICE(obj), "zba", false); > + qdev_prop_set_bit(DEVICE(obj), "zbb", false); > + qdev_prop_set_bit(DEVICE(obj), "zbc", false); > + qdev_prop_set_bit(DEVICE(obj), "zbs", false); > } > > static void rv128_base_cpu_init(Object *obj) > @@ -211,6 +219,10 @@ static void rv32_sifive_u_cpu_init(Object *obj) > CPURISCVState *env = &RISCV_CPU(obj)->env; > set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); > set_priv_version(env, PRIV_VERSION_1_10_0); > + qdev_prop_set_bit(DEVICE(obj), "zba", false); > + qdev_prop_set_bit(DEVICE(obj), "zbb", false); > + qdev_prop_set_bit(DEVICE(obj), "zbc", false); > + qdev_prop_set_bit(DEVICE(obj), "zbs", false); > } > > static void rv32_sifive_e_cpu_init(Object *obj) > @@ -219,6 +231,10 @@ static void rv32_sifive_e_cpu_init(Object *obj) > set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU); > set_priv_version(env, PRIV_VERSION_1_10_0); > qdev_prop_set_bit(DEVICE(obj), "mmu", false); > + qdev_prop_set_bit(DEVICE(obj), "zba", false); > + qdev_prop_set_bit(DEVICE(obj), "zbb", false); > + qdev_prop_set_bit(DEVICE(obj), "zbc", false); > + qdev_prop_set_bit(DEVICE(obj), "zbs", false); > } > > static void rv32_ibex_cpu_init(Object *obj) > @@ -228,6 +244,10 @@ static void rv32_ibex_cpu_init(Object *obj) > set_priv_version(env, PRIV_VERSION_1_10_0); > qdev_prop_set_bit(DEVICE(obj), "mmu", false); > qdev_prop_set_bit(DEVICE(obj), "x-epmp", true); > + qdev_prop_set_bit(DEVICE(obj), "zba", false); > + qdev_prop_set_bit(DEVICE(obj), "zbb", false); > + qdev_prop_set_bit(DEVICE(obj), "zbc", false); > + qdev_prop_set_bit(DEVICE(obj), "zbs", false); > } > > static void rv32_imafcu_nommu_cpu_init(Object *obj) > @@ -237,6 +257,10 @@ static void rv32_imafcu_nommu_cpu_init(Object *obj) > set_priv_version(env, PRIV_VERSION_1_10_0); > set_resetvec(env, DEFAULT_RSTVEC); > qdev_prop_set_bit(DEVICE(obj), "mmu", false); > + qdev_prop_set_bit(DEVICE(obj), "zba", false); > + qdev_prop_set_bit(DEVICE(obj), "zbb", false); > + qdev_prop_set_bit(DEVICE(obj), "zbc", false); > + qdev_prop_set_bit(DEVICE(obj), "zbs", false); > } > #endif > > -- > 2.17.1 > >
