On Wed, May 18, 2022 at 10:50 PM Hongren (Zenithal) Zheng <i...@zenithal.me> wrote: > > Zicsr/Zifencei is not in 'I' since ISA version 20190608, > thus to fully express the capability of the CPU, > they should be exposed in isa_string. > > Signed-off-by: Hongren (Zenithal) Zheng <i...@zenithal.me>
Thanks! Applied to riscv-to-apply.next Alistair > --- > target/riscv/cpu.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 6d01569cad..61fa9b97a4 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -1027,6 +1027,8 @@ static void riscv_isa_string_ext(RISCVCPU *cpu, char > **isa_str, int max_str_len) > * extensions by an underscore. > */ > struct isa_ext_data isa_edata_arr[] = { > + ISA_EDATA_ENTRY(zicsr, ext_icsr), > + ISA_EDATA_ENTRY(zifencei, ext_ifencei), > ISA_EDATA_ENTRY(zfh, ext_zfh), > ISA_EDATA_ENTRY(zfhmin, ext_zfhmin), > ISA_EDATA_ENTRY(zfinx, ext_zfinx), > -- > 2.35.1 > >