On Thu, May 12, 2022 at 12:47 AM Anup Patel <apa...@ventanamicro.com> wrote: > > This series does fixes and improvements to have nested virtualization > on QEMU RISC-V. > > These patches can also be found in riscv_nested_fixes_v2 branch at: > https://github.com/avpatel/qemu.git > > The RISC-V nested virtualization was tested on QEMU RISC-V using > Xvisor RISC-V which has required hypervisor support to run another > hypervisor as Guest/VM. > > Changes since v1: > - Set write_gva to env->two_stage_lookup which ensures that for > HS-mode to HS-mode trap write_gva is true only for HLV/HSV > instructions > - Included "[PATCH 0/3] QEMU RISC-V priv spec version fixes" > patches in this series for easy review > - Re-worked PATCH7 to force disable extensions if required > priv spec version is not staisfied > - Added new PATCH8 to fix "aia=aplic-imsic" mode of virt machine > > Anup Patel (8): > target/riscv: Fix csr number based privilege checking > target/riscv: Fix hstatus.GVA bit setting for traps taken from HS-mode > target/riscv: Set [m|s]tval for both illegal and virtual instruction > traps > target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt() > target/riscv: Don't force update priv spec version to latest > target/riscv: Add dummy mcountinhibit CSR for priv spec v1.11 or > higher > target/riscv: Force disable extensions if priv spec version does not > match > hw/riscv: virt: Fix interrupt parent for dynamic platform devices
Thanks! I have applied some of these patches to riscv-to-apply.next Alistair > > hw/riscv/virt.c | 25 +++--- > target/riscv/cpu.c | 46 +++++++++- > target/riscv/cpu.h | 8 +- > target/riscv/cpu_bits.h | 3 + > target/riscv/cpu_helper.c | 172 ++++++++++++++++++++++++++++++++++++-- > target/riscv/csr.c | 10 ++- > target/riscv/instmap.h | 41 +++++++++ > target/riscv/translate.c | 17 +++- > 8 files changed, 292 insertions(+), 30 deletions(-) > > -- > 2.34.1 > >
